From latta at snf.stanford.edu Fri Aug 6 10:00:46 2004 From: latta at snf.stanford.edu (Nancy Latta) Date: Fri, 06 Aug 2004 10:00:46 -0700 Subject: SiC wafers in tylanpoly? Message-ID: <4113B93E.8010804@snf.stanford.edu> Folks, I have a request from the MEMS Exchange to deposit poly onto Si and SiC wafers. I don't think that we have done this before. So, can SiC (virgin) wafers go into wbdiff and tylanpoly? Thank you, -Nancy From mcvittie at snf.stanford.edu Fri Aug 6 11:48:10 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Fri, 06 Aug 2004 11:48:10 -0700 Subject: SiC wafers in tylanpoly? References: <4113B93E.8010804@snf.stanford.edu> Message-ID: <4113D26A.571A01E1@snf.stanford.edu> Nancy, Are these new wafers, which have not seen any other processing? If they are, they most likely are ok. I would probably have them use the Silicide bench just in case there is a problem. Jim Nancy Latta wrote: > Folks, > > I have a request from the MEMS Exchange to deposit poly onto Si and SiC > wafers. I don't think that we have done this before. So, can SiC > (virgin) wafers go into wbdiff and tylanpoly? > > Thank you, > > -Nancy -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From latta at snf.stanford.edu Fri Aug 6 12:00:15 2004 From: latta at snf.stanford.edu (Nancy Latta) Date: Fri, 06 Aug 2004 12:00:15 -0700 Subject: SiC wafers in tylanpoly? In-Reply-To: <4113D26A.571A01E1@snf.stanford.edu> References: <4113B93E.8010804@snf.stanford.edu> <4113D26A.571A01E1@snf.stanford.edu> Message-ID: <4113D53F.10302@snf.stanford.edu> Hi Jim, They are described as virgin. One point, we generally do not allow wafers cleaned at wbsilicide into tylanpoly; EE410 excepted. Sound ok, all? -Nancy Jim McVittie wrote: >Nancy, > >Are these new wafers, which have not seen any other processing? If they >are, they most likely are ok. I would probably have them use the Silicide >bench just in case there is a problem. > Jim > >Nancy Latta wrote: > > > >>Folks, >> >>I have a request from the MEMS Exchange to deposit poly onto Si and SiC >>wafers. I don't think that we have done this before. So, can SiC >>(virgin) wafers go into wbdiff and tylanpoly? >> >>Thank you, >> >>-Nancy >> >> From mcvittie at snf.stanford.edu Mon Aug 9 11:57:15 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Mon, 09 Aug 2004 11:57:15 -0700 Subject: SiC wafers in tylanpoly and WBSilicide References: <4113B93E.8010804@snf.stanford.edu> <4113D26A.571A01E1@snf.stanford.edu> <4113D53F.10302@snf.stanford.edu> Message-ID: <4117C90B.E44EAAC1@snf.stanford.edu> Nancy, Now that we have a quick way of measuring lifetime uising the SCA2500, I am hopeful that we have a means of comparing our two cleaning benches. I expect that once we have hard numbers, we will be able to open up the Silicide bench for more applications. But I first have to prove that the SCA2500 can do what we need. I was hoping to use the SCA to directly measure lifetime after cleaning but before oxidation. But in reading the manual I see that the SCA can only measure lifetimes down to 20 us, which is probably too long for wafers with chemical oxides coming out of cleaning. As always with lifetime measurements, there is the issue of starting wafers. I want to start some tests this week to see how useful this tool is. Jim . Nancy Latta wrote: > Hi Jim, > > They are described as virgin. One point, we generally do not allow > wafers cleaned at wbsilicide into tylanpoly; EE410 excepted. > > Sound ok, all? > > -Nancy > > Jim McVittie wrote: > > >Nancy, > > > >Are these new wafers, which have not seen any other processing? If they > >are, they most likely are ok. I would probably have them use the Silicide > >bench just in case there is a problem. > > Jim > > > >Nancy Latta wrote: > > > > > > > >>Folks, > >> > >>I have a request from the MEMS Exchange to deposit poly onto Si and SiC > >>wafers. I don't think that we have done this before. So, can SiC > >>(virgin) wafers go into wbdiff and tylanpoly? > >> > >>Thank you, > >> > >>-Nancy > >> > >> -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From lanzhangus at yahoo.com Tue Aug 10 17:07:16 2004 From: lanzhangus at yahoo.com (Lan Zhang) Date: Tue, 10 Aug 2004 17:07:16 -0700 (PDT) Subject: Annealing Lithium Tantalate at Tylan4 Message-ID: <20040811000716.80114.qmail@web50509.mail.yahoo.com> Hello All, I would like to get approval to anneal lithium tantalate wafers in air at 620C with Tylan4(gold contaminated). Please let me know if that is OK. Thanks, Lan --------------------------------- Do you Yahoo!? New and Improved Yahoo! Mail - 100MB free storage! -------------- next part -------------- An HTML attachment was scrubbed... URL: From mcvittie at snf.stanford.edu Tue Aug 10 18:12:57 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Tue, 10 Aug 2004 18:12:57 -0700 Subject: Annealing Lithium Tantalate at Tylan4 References: <20040811000716.80114.qmail@web50509.mail.yahoo.com> Message-ID: <41197299.4778CB05@snf.stanford.edu> All, I propose restricting Tylan #4 to Si and Quartz wafers. If we do not, we will get everything under the sun. This tube is really intended to support the other processing done in our lab where there is a metal or other stable material on the wafer, which keeps it out of the other Tylan tubes. I thought we had high temperature air furnace in the saw room that could be used for this application. Jim Lan Zhang wrote: > Hello All, I would like to get approval to anneal lithium tantalate > wafers in air at 620C with Tylan4(gold contaminated). Please let me > know if that is OK. Thanks,Lan > ----------------------------------------------------------------------- > Do you Yahoo!? > New and Improved Yahoo! Mail - 100MB free storage! -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From mtang at snf.stanford.edu Wed Aug 11 06:44:50 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 11 Aug 2004 06:44:50 -0700 Subject: Annealing Lithium Tantalate at Tylan4 References: <20040811000716.80114.qmail@web50509.mail.yahoo.com> <41197299.4778CB05@snf.stanford.edu> Message-ID: <411A22D2.346ECCAF@snf.stanford.edu> Hi Jim -- Your proposal sounds fine to me. I think, however, that this request is for silicon wafers which just have this unusual film deposited on them. Does this count? By the way, we did have two furnaces in the saw room. One appears to have some irreparable damage to the electronics. The other one's elements have been burnt out. I've been meaning to look into a repair kit for the second one (they sell them, I don't know yet exactly what's in them or if they make one for the specific model we have.) Sigh... I should get on it! Mary Jim McVittie wrote: > All, > > I propose restricting Tylan #4 to Si and Quartz wafers. If we do not, > we will get everything under the sun. This tube is really intended to > support the other processing done in our lab where there is a metal or > other stable material on the wafer, which keeps it out of the other > Tylan tubes. > > I thought we had high temperature air furnace in the saw room that > could be used for this application. > > Jim > > > Lan Zhang wrote: > >> Hello All, I would like to get approval to anneal lithium tantalate >> wafers in air at 620C with Tylan4(gold contaminated). Please let me >> know if that is OK. Thanks,Lan >> --------------------------------------------------------------------- >> Do you Yahoo!? >> New and Improved Yahoo! Mail - 100MB free storage! > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mcvittie at snf.stanford.edu Wed Aug 11 08:57:04 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Wed, 11 Aug 2004 08:57:04 -0700 Subject: Annealing Lithium Tantalate at Tylan4 References: <20040811000716.80114.qmail@web50509.mail.yahoo.com> <41197299.4778CB05@snf.stanford.edu> <411A22D2.346ECCAF@snf.stanford.edu> Message-ID: <411A41D0.EB7BC2DB@snf.stanford.edu> Mary, If the users has Si wafers with a lithium tantalate film them, I agree they would qualify. One other issue is the stability of the film. The last thing we want is for someone to evaporate a film in the tube. For films that we are not familar with, we need some info on its stability in terms of not coming off in the furnace. Jim Mary Tang wrote: > Hi Jim -- > > Your proposal sounds fine to me. I think, however, that this request > is for silicon wafers which just have this unusual film deposited on > them. Does this count? > > By the way, we did have two furnaces in the saw room. One appears to > have some irreparable damage to the electronics. The other one's > elements have been burnt out. I've been meaning to look into a repair > kit for the second one (they sell them, I don't know yet exactly > what's in them or if they make one for the specific model we have.) > Sigh... I should get on it! > > Mary > > Jim McVittie wrote: > >> All, >> >> I propose restricting Tylan #4 to Si and Quartz wafers. If we do >> not, we will get everything under the sun. This tube is really >> intended to support the other processing done in our lab where there >> is a metal or other stable material on the wafer, which keeps it out >> of the other Tylan tubes. >> >> I thought we had high temperature air furnace in the saw room that >> could be used for this application. >> >> Jim >> >> >> Lan Zhang wrote: >> >> > Hello All, I would like to get approval to anneal lithium tantalate >> > wafers in air at 620C with Tylan4(gold contaminated). Please let >> > me know if that is OK. Thanks,Lan >> > -------------------------------------------------------------------- >> > Do you Yahoo!? >> > New and Improved Yahoo! Mail - 100MB free storage! >> > -- > Mary X. Tang, Ph.D. > Stanford Nanofabrication Facility > CIS Room 136, Mail Code 4070 > Stanford, CA 94305 > (650)723-9980 > mtang at stanford.edu > http://snf.stanford.edu > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From mtang at snf.stanford.edu Wed Aug 11 13:46:57 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 11 Aug 2004 13:46:57 -0700 Subject: Annealing Lithium Tantalate at Tylan4 References: <20040811000716.80114.qmail@web50509.mail.yahoo.com> Message-ID: <411A85C1.ADC9DEA8@snf.stanford.edu> Hi Lan -- Do you have more information about your wafers and material? Are they silicon-based? Do you wafers contain any other unusual films? We'd like to make sure that any material that goes into tylan4 does not volatilize or degrade at processing temperature. Do you have any information about the behavior of lithium tantalate under these conditions? Thanks, Mary Lan Zhang wrote: > Hello All, I would like to get approval to anneal lithium tantalate > wafers in air at 620C with Tylan4(gold contaminated). Please let me > know if that is OK. Thanks,Lan > ----------------------------------------------------------------------- > Do you Yahoo!? > New and Improved Yahoo! Mail - 100MB free storage! -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at snf.stanford.edu Wed Aug 11 14:17:06 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 11 Aug 2004 14:17:06 -0700 Subject: [Fwd: Re: Annealing Lithium Tantalate at Tylan4] Message-ID: <411A8CD2.C42B9E26@snf.stanford.edu> Hi all -- Sorry, I was wrong -- it's not a film on silicon, but crystalline material. What do you think? Mary -------- Original Message -------- Subject: Re: Annealing Lithium Tantalate at Tylan4 Date: Wed, 11 Aug 2004 14:11:41 -0700 (PDT) From: Lan Zhang To: Mary Tang Hi Mary, I attached MSDS for lithium tantalate, which is on SNF MSDS file as well. The wafer is lithium tantalate (LiTaO3) and no film is on that. Lithium Tanalate is very stable upto 1200C or higher. Let me know if you have more question. Thanks,Lan Mary Tang wrote: Hi Lan -- Do you have more information about your wafers and material? Are they silicon-based? Do you wafers contain any other unusual films? We'd like to make sure that any material that goes into tylan4 does not volatilize or degrade at processing temperature. Do you have any information about the behavior of lithium tantalate under these conditions? Thanks, Mary Lan Zhang wrote: > Hello All, I would like to get approval to anneal lithium > tantalate wafers in air at 620C with Tylan4(gold > contaminated). Please let me know if that is OK. > Thanks,Lan > ------------------------------------------------------------- > Do you Yahoo!? > New and Improved Yahoo! Mail - 100MB free storage! -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: LTMSDS.pdf Type: application/pdf Size: 141666 bytes Desc: LTMSDS.pdf URL: From mcvittie at snf.stanford.edu Wed Aug 11 15:27:54 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Wed, 11 Aug 2004 15:27:54 -0700 Subject: [Fwd: Re: Annealing Lithium Tantalate at Tylan4] References: <411A8CD2.C42B9E26@snf.stanford.edu> Message-ID: <411A9D6A.511A2320@snf.stanford.edu> Mary, As I said, I am biased toward Si based processing. How much does Lan use our Lab? Jim Mary Tang wrote: > Hi all -- > > Sorry, I was wrong -- it's not a film on silicon, but crystalline > material. What do you think? > > Mary > > -------- Original Message -------- > Subject: Re: Annealing Lithium Tantalate at Tylan4 Date: Wed, 11 Aug 2004 14:11:41 -0700 (PDT) From: Lan Zhang To: Mary Tang > > Hi Mary, I attached MSDS for lithium tantalate, which is on SNF MSDS > file as well. The wafer is lithium tantalate (LiTaO3) and no film is > on that. Lithium Tanalate is very stable upto 1200C or higher. Let > me know if you have more question. Thanks,Lan > > Mary Tang wrote: > > Hi Lan -- > > Do you have more information about your wafers and > material? Are they silicon-based? Do you wafers contain > any other unusual films? We'd like to make sure that any > material that goes into tylan4 does not volatilize or > degrade at processing temperature. Do you have any > information about the behavior of lithium tantalate under > these conditions? > > Thanks, > > Mary > > Lan Zhang wrote: > > > Hello All, I would like to get approval to anneal lithium > > tantalate wafers in air at 620C with Tylan4(gold > > contaminated). Please let me know if that is OK. > > Thanks,Lan > > ----------------------------------------------------------- > > Do you Yahoo!? > > New and Improved Yahoo! Mail - 100MB free storage! > > -- > Mary X. Tang, Ph.D. > Stanford Nanofabrication Facility > CIS Room 136, Mail Code 4070 > Stanford, CA 94305 > (650)723-9980 > mtang at stanford.edu > http://snf.stanford.edu > > __________________________________________________ > Do You Yahoo!? > Tired of spam? Yahoo! Mail has the best spam protection around > http://mail.yahoo.com -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From mtang at snf.stanford.edu Wed Aug 11 15:39:53 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 11 Aug 2004 15:39:53 -0700 Subject: [Fwd: Re: Annealing Lithium Tantalate at Tylan4] References: <411A8CD2.C42B9E26@snf.stanford.edu> <411A9D6A.511A2320@snf.stanford.edu> Message-ID: <411AA039.CCCC48FF@snf.stanford.edu> A bit (he's from Coherent.) However, I just sent an email asking if he could use our muffle furnace in the wafersaw room and he said it would be fine. Now, I need to fix it (I just ordered new elements, which should hopefully do the trick.) I will email Lan and ask if him to wait for us to repair the little furnace. Thanks, Mary Jim McVittie wrote: > Mary, > > As I said, I am biased toward Si based processing. How much does Lan > use our Lab? > > Jim > > Mary Tang wrote: > >> Hi all -- >> >> Sorry, I was wrong -- it's not a film on silicon, but crystalline >> material. What do you think? >> >> Mary >> >> -------- Original Message -------- >> Subject: Re: Annealing Lithium Tantalate at Tylan4 Date: Wed, 11 Aug 2004 14:11:41 -0700 (PDT) From: Lan Zhang To: Mary Tang >> >> Hi Mary, I attached MSDS for lithium tantalate, which is on SNF >> MSDS file as well. The wafer is lithium tantalate (LiTaO3) and no >> film is on that. Lithium Tanalate is very stable upto 1200C or >> higher. Let me know if you have more question. Thanks,Lan >> >> Mary Tang wrote: >> >> Hi Lan -- >> >> Do you have more information about your wafers and >> material? Are they silicon-based? Do you wafers contain >> any other unusual films? We'd like to make sure that any >> material that goes into tylan4 does not volatilize or >> degrade at processing temperature. Do you have any >> information about the behavior of lithium tantalate under >> these conditions? >> >> Thanks, >> >> Mary >> >> Lan Zhang wrote: >> >> > Hello All, I would like to get approval to anneal lithium >> > tantalate wafers in air at 620C with Tylan4(gold >> > contaminated). Please let me know if that is OK. >> > Thanks,Lan >> > ---------------------------------------------------------- >> > Do you Yahoo!? >> > New and Improved Yahoo! Mail - 100MB free storage! >> >> -- >> Mary X. Tang, Ph.D. >> Stanford Nanofabrication Facility >> CIS Room 136, Mail Code 4070 >> Stanford, CA 94305 >> (650)723-9980 >> mtang at stanford.edu >> http://snf.stanford.edu >> >> __________________________________________________ >> Do You Yahoo!? >> Tired of spam? Yahoo! Mail has the best spam protection around >> http://mail.yahoo.com > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From kimsangb at stanford.edu Thu Aug 12 20:52:56 2004 From: kimsangb at stanford.edu (SangBum Kim) Date: Thu, 12 Aug 2004 20:52:56 -0700 Subject: Tylan4 for annealing the bonded Si wafers Message-ID: <002401c480e9$0501dd00$59b50c80@LocalHost> Dear SpecMat, I would like to use Tylan4 for annealing the bonded Si wafers. The processes that the bonded Si wafers went through are 1) Cleaning at the diffusion wet bench 2) Oxygen plasma etching in Drytek2 3) Spin, Rinse and Dry 4) Wafers are bonded manually at room temperature 5) Tylan4 (recipe 400AN) Please let me know whether I can use this process. Thanks, SangBum Kim (coral login name:kimsangb) -------------- next part -------------- An HTML attachment was scrubbed... URL: From jimkruger at yahoo.com Mon Aug 16 11:07:28 2004 From: jimkruger at yahoo.com (jim kruger) Date: Mon, 16 Aug 2004 11:07:28 -0700 (PDT) Subject: Request for Yttrium use Message-ID: <20040816180728.15193.qmail@web40905.mail.yahoo.com> Request for approval of Y (Yttrium) deposition in Metallica Requestor: Jim Kruger (jimkruger at snf.stanford.edu) Phone: 650-726-7260 e-mail: jimkruger at yahoo.com Advisor: Cymer (John Viatella) Vendor: ACIalloys.com 1985 Las Plumas Avenue San Jose, CA 95133 (408) 259-7337 Phone (408) 729-0277 Fax Vendor e-mail: acialloys.com This material is a candidate for use in the Multi-Layer-Mirrors that will be used for EUV Lithography. Work at SNF would be limited to sputter deposition in Metallica, determination of film thickness by Dektak, Zygo , manual 4-point probe and possibly AFM. Wafers are to be sawed into coupons for tests outside of SNF. Since Yttrium (Y) is already in use in SNF ( Innotec), I don?t believe there are any issues. The vapor pressure of Y is very similar to that of Si. Finely divided particles of Y are reported as igniting in air above 400 C, but thin films for Multi-layer-mirrors are reported as stable. Material form: Solid I propose to bring one sputter target (1? dia. x 0.125?) into SNF and deposit 10 to 100 nm on 8 or 12 wafers. Beyond film measurements and sawing, only annealing tests (hot plate or Blue M oven) are planned. __________________________________ Do you Yahoo!? Yahoo! Mail - 50x more storage than other providers! http://promotions.yahoo.com/new_mail From mcvittie at snf.stanford.edu Tue Aug 17 12:46:47 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Tue, 17 Aug 2004 12:46:47 -0700 Subject: Request for Yttrium use References: <20040816180728.15193.qmail@web40905.mail.yahoo.com> Message-ID: <412260A7.4B6959DC@snf.stanford.edu> All, I see no problem in using Y in the Metalica. There are no safety issues (ratings: 0 0 1) that I can fine and it has a relatively low vapor pressure (1e-8T at 830C). Sputtering is the preferred method of deposition for this metal. Jim jim kruger wrote: > Request for approval of Y (Yttrium) deposition in > Metallica > > Requestor: Jim Kruger (jimkruger at snf.stanford.edu) > Phone: 650-726-7260 > e-mail: jimkruger at yahoo.com > Advisor: Cymer (John Viatella) > > Vendor: > ACIalloys.com > 1985 Las Plumas Avenue > San Jose, CA 95133 > (408) 259-7337 Phone > (408) 729-0277 Fax > > Vendor e-mail: acialloys.com > > This material is a candidate for use in the > Multi-Layer-Mirrors that will be used for EUV > Lithography. > Work at SNF would be limited to sputter deposition in > Metallica, determination of film thickness by Dektak, > Zygo , manual 4-point probe and possibly AFM. Wafers > are to be sawed into coupons for tests outside of SNF. > > Since Yttrium (Y) is already in use in SNF ( Innotec), > I don?t believe there are any issues. The vapor > pressure of Y is very similar to that of Si. Finely > divided particles of Y are reported as igniting in air > above 400 C, but thin films for Multi-layer-mirrors > are reported as stable. > > Material form: Solid > I propose to bring one sputter target (1? dia. x > 0.125?) into SNF and deposit 10 to 100 nm on 8 or 12 > wafers. Beyond film measurements and sawing, only > annealing tests (hot plate or Blue M oven) are > planned. > > > __________________________________ > Do you Yahoo!? > Yahoo! Mail - 50x more storage than other providers! > http://promotions.yahoo.com/new_mail -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From latta at snf.stanford.edu Wed Aug 18 09:36:01 2004 From: latta at snf.stanford.edu (Nancy Latta) Date: Wed, 18 Aug 2004 09:36:01 -0700 Subject: Couple of requests from MEMS Exchange Message-ID: <41238571.80106@snf.stanford.edu> Folks, The MEMS Exchange people has asked me to ask about two etch proccesses; 1) They have a customer that has nitride over Moly/carbon on a Si substrate. They want to use a Cl process to etch the nitride and expose the Moly/carbon. Any chance pquest can be used? They do not want to use a flourine process. 2) Another customer wants to etch Al/3%Ti off a SiC substrate. I need to check about the cleanliness of the sputtered metals, but the first problem is that the samples are 2 inch. They are suggesting that we mount them to a 4 in wafer and use p5000. Thanks for your reply, -Nancy From edmyers at stanford.edu Wed Aug 18 09:59:00 2004 From: edmyers at stanford.edu (Ed Myers) Date: Wed, 18 Aug 2004 09:59:00 -0700 Subject: What is Semi-Clean Message-ID: <6.0.1.1.2.20040818091851.01b7a2f0@edmyers.pobox.stanford.edu> SpecMat Committee, We are getting close having a couple of students spearhead the use of the SCT sputter. This is great, since they can take the lead at understanding the influence of RF and heat during deposition. The only conflict I see is the materials they want to use is outside of the current definition of Semi-Clean metals. Metals that are currently being requested include: Ni, Mo, Hf and reactively sputtered TiN. These materials and metals such as Co have been successfully introduced into high volume semiconductor manufacturing facilities. There is also an increase in the use conductive metal oxides, such as Ru and Ir for contacting high dielectric constant materials. If we allow these materials in a Semi-Clean sputter, we will have opened a cascading effect for the balance of the Semi-Clean tool set. I think we should take this opportunity to revisit the what metals should comprise the Semi-Clean list. Ed Myers >X-Sieve: CMU Sieve 2.2 >Delivered-To: emyers at snf.stanford.edu >Date: Mon, 16 Aug 2004 08:49:57 -0700 (PDT) >From: Abhijit Pethe >To: emyers at snf.stanford.edu >Subject: Request for training and use on the SCT > > >Hi Ed, > >My name is Abhijit and I am working with Prof. Saraswat on the properties >on the Metal-Germnanium Ohmic Contacts. The cleanliness of the apparatus >and the substrate is extermely crucial for studying these >interfaces. We would hence want to use an equipment belonging to the >semi-clean category as opposed to the gold-contaminated Innotec. > >We plan to study the following metals >1. Ni >2. Hf/W (Hf capped with W) >3. Ti/TiN > >It would be great if you could train me on the system once it is available >for use. Please let me know if there is any other information I need to >supply. > >Thanks >Abhijit From mcvittie at snf.stanford.edu Wed Aug 18 11:24:00 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Wed, 18 Aug 2004 11:24:00 -0700 Subject: What is Semi-Clean References: <6.0.1.1.2.20040818091851.01b7a2f0@edmyers.pobox.stanford.edu> Message-ID: <41239EBF.5B12F2BB@snf.stanford.edu> Ed, Here my initial thoughts. Mike Deal and I need to get together and consolidate our thoughts on the tool. Semiclean is a term that Margaret Prisbe came up some years back. For the SCT system, it means that we will only allow metals, wafers and procedures compatible with CMOS devices. In terms of metals, the list use to be pretty short, however with the push toward hi-k and metal gates the list has gotten longer and more uncertain. The uncertainty means that we are going be trying out new metals to see how well they work from a CMOS device standpoint and how well we can keep them from getting into or cross-contaminating metal depositions where we do not want them. An important issue with the SCT is that it is a tool where we want to get reproducible device properties. The initial concern is work function control, which means interface control. This requirement means that, like the Balzer, we probably will not allow organics. Thick depositions may also be a problem. The SCT is the replacement for the Balzer, which was a device research tool. The main difference the SCT and Balzers is that the target cost is much lower and we are not restricted by the needs of the Physics group. The restrictions will now be set by the CMOS device needs. In terms of wafers, no gold (or sodium like metals) contaminated wafers will be allowed. Because the importance of interface control, organics on wafers will be restricted. Other problem metals will be prohibited or have restrictions in terms of sputter etching and heating. In terms of procedures, I am concerned with any procedure that would affect contamination of deposited films or interfaces. Areas of concern are deposition thickness, sputter etching and substrate temperature. Thick depositions cause flaking which increases surface area and cross-contamination. Sputter etching can introduce contamination material from wafers. Finally, heating of substrates can cause contamination problem. At this point I am not sure exactly how these concerns should translate into restrictions. Regarding nitride and oxide deposition, there is no question that we will allow reactive metal nitride deposition in the tool. As for oxide deposition, I think we need some experience with the tool and a device need before addition this capability. Jim Ed Myers wrote: > SpecMat Committee, > > We are getting close having a couple of students spearhead the use of the > SCT sputter. This is great, since they can take the lead at understanding > the influence of RF and heat during deposition. The only conflict I see is > the materials they want to use is outside of the current definition of > Semi-Clean metals. > > Metals that are currently being requested include: Ni, Mo, Hf and > reactively sputtered TiN. These materials and metals such as Co have been > successfully introduced into high volume semiconductor manufacturing > facilities. There is also an increase in the use conductive metal oxides, > such as Ru and Ir for contacting high dielectric constant materials. > > If we allow these materials in a Semi-Clean sputter, we will have opened a > cascading effect for the balance of the Semi-Clean tool set. I think we > should take this opportunity to revisit the what metals should comprise the > Semi-Clean list. > > Ed Myers > > >X-Sieve: CMU Sieve 2.2 > >Delivered-To: emyers at snf.stanford.edu > >Date: Mon, 16 Aug 2004 08:49:57 -0700 (PDT) > >From: Abhijit Pethe > >To: emyers at snf.stanford.edu > >Subject: Request for training and use on the SCT > > > > > >Hi Ed, > > > >My name is Abhijit and I am working with Prof. Saraswat on the properties > >on the Metal-Germnanium Ohmic Contacts. The cleanliness of the apparatus > >and the substrate is extermely crucial for studying these > >interfaces. We would hence want to use an equipment belonging to the > >semi-clean category as opposed to the gold-contaminated Innotec. > > > >We plan to study the following metals > >1. Ni > >2. Hf/W (Hf capped with W) > >3. Ti/TiN > > > >It would be great if you could train me on the system once it is available > >for use. Please let me know if there is any other information I need to > >supply. > > > >Thanks > >Abhijit -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From mtang at snf.stanford.edu Wed Aug 18 16:55:55 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Wed, 18 Aug 2004 16:55:55 -0700 Subject: specmat question References: <002401c48550$bf776f90$59b50c80@LocalHost> Message-ID: <4123EC8B.DBB56DB4@snf.stanford.edu> Hi SangBum -- Sorry for the delay. Tylan4 is now gold-compatible and can be used for the process flow you propose. Your wafers will then be considered gold-contaminated after tylan4 processing. Under these conditions, your process flow is approved. Thanks for your patience -- Mary SangBum Kim wrote: > Dear Dr. Tang, I have requested SpecMat to approve me to use Tylan4 > last Thursday and haven't received any response yet. Could you tell me > the status of my request? I am including the original message I sent > to SpecMat at the end. Thank you very much! Sincerely,SangBum > ----- Original Message ----- > From: SangBum Kim > To: specmat at snf.stanford.eduSent: Thursday, August 12, 2004 8:52 > PMSubject: Tylan4 for annealing the bonded Si wafers > Dear SpecMat, I would like to use Tylan4 for annealing the bonded Si > wafers. The processes that the bonded Si wafers went through are 1) > Cleaning at the diffusion wet bench2) Oxygen plasma etching in > Drytek23) Spin, Rinse and Dry4) Wafers are bonded manually at room > temperature5) Tylan4 (recipe 400AN) Please let me know whether I can > use this process. Thanks,SangBum Kim (coral login name:kimsangb) -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From latta at snf.stanford.edu Wed Aug 25 13:44:11 2004 From: latta at snf.stanford.edu (Nancy Latta) Date: Wed, 25 Aug 2004 13:44:11 -0700 Subject: [Fwd: Couple of requests from MEMS Exchange] Message-ID: <412CFA1B.1010905@snf.stanford.edu> Folks, I sent these requests to Spec Mat a week ago. Any progress? -------------- next part -------------- An embedded message was scrubbed... From: Nancy Latta Subject: Couple of requests from MEMS Exchange Date: Wed, 18 Aug 2004 09:36:01 -0700 Size: 1069 URL: From mtang at snf.stanford.edu Tue Aug 31 07:03:25 2004 From: mtang at snf.stanford.edu (Mary Tang) Date: Tue, 31 Aug 2004 07:03:25 -0700 Subject: [Fwd: Couple of requests from MEMS Exchange] References: <412CFA1B.1010905@snf.stanford.edu> Message-ID: <4134852D.C8519C41@snf.stanford.edu> I think these are questions for Jim... and I've a couple more to add regarding logistics... 1. I don't believe that Nancy (and please correct me if I'm wrong, Nancy) is going to feel comfortable doing this etch on the pquest. Is there any chance that you or someone you feel is knowledgeable about the pquest could do this? If not, then I suggest that MEMS exchange try to find another site to do this. Nancy -- if this could be done here, could we get more info from the customer as to what the process requirements are? (I presume that Moly/C are pretty robust against Cl, but no idea how much, and it seems they are concerned if they want to avoid Fl... Is Moly/C a shiny reflective substrate? I mean, can we use the nanospec to measure nitride?) 2. Can smaller pieces be mounted on 4" wafers for processing in the P5000? I know this has been done, but gather that it's on a case-by-case basis? Are carbon dots acceptable? I think you had mentioned that your technical contacts at Applied used a certain adhesive... is this something that's been investigated here? Jim -- what do you think? Mary Nancy Latta wrote: > Folks, > > I sent these requests to Spec Mat a week ago. Any progress? > > ------------------------------------------------------------------------ > > Subject: Couple of requests from MEMS Exchange > Date: Wed, 18 Aug 2004 09:36:01 -0700 > From: Nancy Latta > To: specmat at snf.stanford.edu > > Folks, > > The MEMS Exchange people has asked me to ask about two etch proccesses; > 1) They have a customer that has nitride over Moly/carbon on a Si > substrate. They want to use a Cl process to etch the nitride and expose > the Moly/carbon. Any chance pquest can be used? They do not want to > use a flourine process. > > 2) Another customer wants to etch Al/3%Ti off a SiC substrate. I need > to check about the cleanliness of the sputtered metals, but the first > problem is that the samples are 2 inch. They are suggesting that we > mount them to a 4 in wafer and use p5000. > > Thanks for your reply, > > -Nancy -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mcvittie at snf.stanford.edu Tue Aug 31 10:48:23 2004 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Tue, 31 Aug 2004 10:48:23 -0700 Subject: [Fwd: Couple of requests from MEMS Exchange] References: <412CFA1B.1010905@snf.stanford.edu> <4134852D.C8519C41@snf.stanford.edu> Message-ID: <4134B9E7.4198BC98@snf.stanford.edu> Mary, Regarding item #1, I have never intentionally etched silicon nitride with a chlorine based process. While Mo etches best in an F based etch, it should etch at a slower rate in a Cl based etch. I say this because the boiling points of MoF5 and MoCl5 are 35 C and 268C, respectively. Note that the boiling point of TiF4 is 284C and we often etch Ti is SF6 plasmas. If the requestor has a ref for nitride etching in Cl2, we can look into doing it in the Pquest. Regarding item #2, we have etched pieces in the Al chamber on the P5000. However, we have not tried to mount 2? wafers onto 4?. The mounting process uses doublesided carbon tape to attach the pieces and resist to seal the edges. It is a pain to get off all the tape residue after the etch. I am willing to try other mounting methods but one does need good thermal contact between the carrier wafer and pieces to get good etch results. Jim Mary Tang wrote: > I think these are questions for Jim... and I've a couple more to add > regarding logistics... > > 1. I don't believe that Nancy (and please correct me if I'm wrong, Nancy) is > going to feel comfortable doing this etch on the pquest. Is there any chance > that you or someone you feel is knowledgeable about the pquest could do this? > If not, then I suggest that MEMS exchange try to find another site to do > this. Nancy -- if this could be done here, could we get more info from the > customer as to what the process requirements are? (I presume that Moly/C are > pretty robust against Cl, but no idea how much, and it seems they are > concerned if they want to avoid Fl... Is Moly/C a shiny reflective > substrate? I mean, can we use the nanospec to measure nitride?) > > 2. Can smaller pieces be mounted on 4" wafers for processing in the P5000? I > know this has been done, but gather that it's on a case-by-case basis? Are > carbon dots acceptable? I think you had mentioned that your technical > contacts at Applied used a certain adhesive... is this something that's been > investigated here? > > Jim -- what do you think? > > Mary > > Nancy Latta wrote: > > > Folks, > > > > I sent these requests to Spec Mat a week ago. Any progress? > > > > ------------------------------------------------------------------------ > > > > Subject: Couple of requests from MEMS Exchange > > Date: Wed, 18 Aug 2004 09:36:01 -0700 > > From: Nancy Latta > > To: specmat at snf.stanford.edu > > > > Folks, > > > > The MEMS Exchange people has asked me to ask about two etch proccesses; > > 1) They have a customer that has nitride over Moly/carbon on a Si > > substrate. They want to use a Cl process to etch the nitride and expose > > the Moly/carbon. Any chance pquest can be used? They do not want to > > use a flourine process. > > > > 2) Another customer wants to etch Al/3%Ti off a SiC substrate. I need > > to check about the cleanliness of the sputtered metals, but the first > > problem is that the samples are 2 inch. They are suggesting that we > > mount them to a 4 in wafer and use p5000. > > > > Thanks for your reply, > > > > -Nancy > > -- > Mary X. Tang, Ph.D. > Stanford Nanofabrication Facility > CIS Room 136, Mail Code 4070 > Stanford, CA 94305 > (650)723-9980 > mtang at stanford.edu > http://snf.stanford.edu -------------- next part -------------- A non-text attachment was scrubbed... Name: mcvittie.vcf Type: text/x-vcard Size: 422 bytes Desc: Card for Jim McVittie URL: From latta at snf.stanford.edu Tue Aug 31 11:06:15 2004 From: latta at snf.stanford.edu (Nancy Latta) Date: Tue, 31 Aug 2004 11:06:15 -0700 Subject: [Fwd: Couple of requests from MEMS Exchange] In-Reply-To: <4134B9E7.4198BC98@snf.stanford.edu> References: <412CFA1B.1010905@snf.stanford.edu> <4134852D.C8519C41@snf.stanford.edu> <4134B9E7.4198BC98@snf.stanford.edu> Message-ID: <4134BE17.1080508@snf.stanford.edu> Thanks, All, for your consideration of this request. During today's conference call, the folks at the MEMS Exchange decided to look elsewhere for etching for this customer. Again, thanks, -Nancy Jim McVittie wrote: >Mary, > >Regarding item #1, I have never intentionally etched silicon nitride with a >chlorine based process. While Mo etches best in an F based etch, it should etch at >a slower rate in a Cl based etch. I say this because the boiling points of MoF5 >and MoCl5 are 35 C and 268C, respectively. Note that the boiling point of TiF4 is >284C and we often etch Ti is SF6 plasmas. If the requestor has a ref for nitride >etching in Cl2, we can look into doing it in the Pquest. > >Regarding item #2, we have etched pieces in the Al chamber on the P5000. However, >we have not tried to mount 2? wafers onto 4?. The mounting process uses >doublesided carbon tape to attach the pieces and resist to seal the edges. It is a >pain to get off all the tape residue after the etch. I am willing to try other >mounting methods but one does need good thermal contact between the carrier wafer >and pieces to get good etch results. > > Jim > > >Mary Tang wrote: > > > >>I think these are questions for Jim... and I've a couple more to add >>regarding logistics... >> >>1. I don't believe that Nancy (and please correct me if I'm wrong, Nancy) is >>going to feel comfortable doing this etch on the pquest. Is there any chance >>that you or someone you feel is knowledgeable about the pquest could do this? >>If not, then I suggest that MEMS exchange try to find another site to do >>this. Nancy -- if this could be done here, could we get more info from the >>customer as to what the process requirements are? (I presume that Moly/C are >>pretty robust against Cl, but no idea how much, and it seems they are >>concerned if they want to avoid Fl... Is Moly/C a shiny reflective >>substrate? I mean, can we use the nanospec to measure nitride?) >> >>2. Can smaller pieces be mounted on 4" wafers for processing in the P5000? I >>know this has been done, but gather that it's on a case-by-case basis? Are >>carbon dots acceptable? I think you had mentioned that your technical >>contacts at Applied used a certain adhesive... is this something that's been >>investigated here? >> >> Jim -- what do you think? >> >>Mary >> >>Nancy Latta wrote: >> >> >> >>>Folks, >>> >>>I sent these requests to Spec Mat a week ago. Any progress? >>> >>> ------------------------------------------------------------------------ >>> >>>Subject: Couple of requests from MEMS Exchange >>>Date: Wed, 18 Aug 2004 09:36:01 -0700 >>>From: Nancy Latta >>>To: specmat at snf.stanford.edu >>> >>>Folks, >>> >>>The MEMS Exchange people has asked me to ask about two etch proccesses; >>>1) They have a customer that has nitride over Moly/carbon on a Si >>>substrate. They want to use a Cl process to etch the nitride and expose >>>the Moly/carbon. Any chance pquest can be used? They do not want to >>>use a flourine process. >>> >>>2) Another customer wants to etch Al/3%Ti off a SiC substrate. I need >>>to check about the cleanliness of the sputtered metals, but the first >>>problem is that the samples are 2 inch. They are suggesting that we >>>mount them to a 4 in wafer and use p5000. >>> >>>Thanks for your reply, >>> >>>-Nancy >>> >>> >>-- >>Mary X. Tang, Ph.D. >>Stanford Nanofabrication Facility >>CIS Room 136, Mail Code 4070 >>Stanford, CA 94305 >>(650)723-9980 >>mtang at stanford.edu >>http://snf.stanford.edu >> >>