Spin-on dopant annealing

Amy Lee kone at stanford.edu
Wed Jul 28 23:17:49 PDT 2004

Process flow (either A or B, not including the various diff cleans
required in between the furnace steps):

A. Bare Si wafer -> tylan furnace to grow oxide layer -> tylan poly to
   amorphous Si -> cont'd below


B. Purchased SOI wafer -> cont'd below

A or B -> spin on SOD w/ headway coater -> bake on hot plate for 1hr @
100degC -> RTA or tylan4 to drive in the dopants -> residual film strip
at wbgeneral

I am assuming that the SOD is electronics grade, but I will have to call
and check to be sure.  Otherwise, here is more information from the
vendor about the SOD we are using.  


> -----Original Message-----
> From: Mary Tang [mailto:mtang at snf.stanford.edu]
> Sent: Wednesday, July 28, 2004 4:58 PM
> To: Amy Lee
> Cc: specmat at snf.stanford.edu; dtyeh at stanford.edu
> Subject: Re: Spin-on dopant annealing
> Hi Amy --
> Could you please outline your process flow in more detail?  I think
> SOD is
> often spun on, and then heated to drive dopants to the interface,
> to
> remove the oxide, and then annealed to do drive in.  Is this what you
> proposing to do?  Otherwise, are you proposing to put uncured SOD into
> ag4108?  By the way, the headway is considered gold-contaminated --
> because
> the wafer comes into direct contact with the not-so-clean chuck,
> there
> is a proper wbdiff-type clean afterwards, I don't think it's a good
> to put
> this into the ag4108...
> I don't recall, but is the SOD electronics grade?
> Mary
> Amy Lee wrote:
> > We're interested in putting a bare Si wafer that has been treated
with a
> > spin-on dopant (SOD) in the ag4108 rapid thermal annealer at
> temperatures
> > around 1000degC.  Prior to RTA, the only "non-clean" process the
> will
> > go through is the application of the SOD, which is done on the
> in
> > Litho.  After RTA, the wafer does not need to be put into any clean
> > processing eqpt.
> >
> > Our group already has approval to use the SOD (Emulsitone,
> > film) in the lab (Morgan Mager received the approval).
> >
> > If we can't put it in ag4108, would it be possible to put our wafers
> > Tylan4 furnace instead?
> >
> > Thanks,
> > Amy Lee
> --
> Mary X. Tang, Ph.D.
> Stanford Nanofabrication Facility
> CIS Room 136, Mail Code 4070
> Stanford, CA  94305
> (650)723-9980
> mtang at stanford.edu
> http://snf.stanford.edu

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