High T GaAs processing request
mdeal at stanford.edu
Tue Sep 14 10:53:15 PDT 2004
My concerns are that above about 400C, GaAs outgasses significant arsenic
vapor. When we did high temperature anneals of GaAs (10-15 years ago) in
the range of 700-900C, we had a set of procedures and requirements to
ensure safety. These included:
1. the GaAs must be encapsulated in PECVD silicon oxide or nitride. In
addition, the GaAs was placed between two 4inch Si wafers during the anneal.
2. We had a procedure for pushing and pulling the wafers out of the
furnace, which included using an "elephant" tube at the front during the
pull as well as letting the wafer cool for 1 hour at the front of the
furnace in the cool zone before removing the wafer carrier.
3. Doing periodic arsenic contamination testing, including both wipe tests
on wetbench surfaces and surfaces around the outside of the furnace, as
well as airborne testing around the furnace.
4. A separate GaAs waste bucket was utilized.
We had similar procedures for using the RTA, including buidling an
evacuated enclusure around it.
After the Plummer GaAs research was ended (which I was in charge of and
Robin King helped with), we allowed Prof. Harris' group to use the top PWS
furnace tube for some AlGaAs annealing, but he was responsible for
that. It is my understanding that the PWS furnace stack will be removed
as part of the 6 inch conversion.
As far as using another furnace, in light of the above considerations, I
would be very hesitant to allow high temperature processing of GaAs. I
think we would only allow it if similar procedures were used, including
arsenic contamination analyses, requiring an evacuated chamber around any
furnace, and having an SNF tech be responsible for overseeing the
processing and testing.
At 10:31 AM 9/14/2004, Mary Tang wrote:
>Hi Mike --
>We've got a request from a labmember to do some high T GaAs processing
>in the gaas22 or gaas23 furnaces. It's the Group4 people who are
>requesting this on behalf of a collaborator (and potential new
>labmember). The substrates they would like to bond are silicon carbide
>and GaAs. The collaborator who assures us that he has many years of
>experience doing this and similar bonding processes at Santa Barbara and
>IBM or HP. The process involves encasing the substrates (which will be
>small pieces) in a graphite fixture. They would like to have the
>flexibility of going up to 800 C.
>We have safety concerns. I understand from Dick that he's spoken with
>you about this and that you have similar concerns. Could you describe
>your concerns? Or better yet, give your judgement on the safety issues
>on this process?
>By the way, we thought there may be issues with these furnaces and
>wonder if it might be possible to offer the Thermolyne furnace as an
>alternative, provided they can demonstrate that there are no safety
>concerns with outgassing. Do you think this could be a viable solution?
>Mary X. Tang, Ph.D.
>Stanford Nanofabrication Facility
>CIS Room 136, Mail Code 4070
>Stanford, CA 94305
>mtang at stanford.edu
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