From tparco2002 at yahoo.com  Tue Feb  1 09:13:56 2005
From: tparco2002 at yahoo.com (Tony Parco)
Date: Tue, 1 Feb 2005 09:13:56 -0800 (PST)
Subject: Fwd: Re: Fwd: Re: Alumimum Oxide
Message-ID: <20050201171356.13031.qmail@web52301.mail.yahoo.com>

To SpecMat.

Respectfully request to sputter or evaporate Al2O3 in
metalica or innotec. I would deposit about 100A or
less per wafer (x1 to x3 plus a presputter
conditioning on dummy wafer).  If contamination is an
issue I could sputter a metal target of choice to coat
(>~1000A or more) the sputter cylinder and, as well as
the dummy wafer.

If you need additional information, please don't
hesitate to email me at your earliest convenience.

Thanks,

Tony Parco
Process Development Engineer

Molecular Nanosystems, Inc.
977 Commercial St.
Palo Alto, Ca.  94303

cell # (925)-413-6598
tony at monano.com
--- Jeannie Perez <jperez at snf.stanford.edu> wrote:

> Date: Thu, 27 Jan 2005 14:24:31 -0800
> From: Jeannie Perez <jperez at snf.stanford.edu>
> To: Tony Parco <tparco2002 at yahoo.com>
> Subject: Re: Fwd: Re: Alumimum Oxide
> 
> Hi Tony,
> Same answer as before, you need to send your request
> to the Specmat
> committee. I just talked to Jim Mc Vitte and he said
> it could be done if
> it is a thin layer, but it is a contamination issue
> and only can be done
> with RF sputtering. Never the less, you'll have to
> get an OK from the
> Committee.
> Jeannie
> 
> Tony Parco wrote:
> 
> > Hi Jeannie,
> >
> > Please read message below...is it possible to do
> it in
> > metalica or innotec, if we have a target.
> >
> > Tony
> >
> > --- gu <gu at monano.com> wrote:
> >
> > > Date: Thu, 27 Jan 2005 10:29:59 -0800
> > > From: gu <gu at monano.com>
> > > To: Tony Parco <tparco2002 at yahoo.com>
> > > Subject: Re: Alumimum Oxide
> > >
> > > Hi Tony,
> > >
> > > I mean Al2O3, directly deposit Al2O3 thin films
> with
> > > sputtering or
> > > evaporation. One staff told me last year, it may
> be
> > > possible to deposit
> > > Al2O3 with metalic after modification. Can you
> ask
> > > some senior staff in
> > > CIS the possibility to deposit Al2O3 thin films
> with
> > > sputtering or
> > > evaporation?
> > >
> > > Thanks,
> > > Gu Gang
> > >
> > >
> > >
> > > Tony Parco wrote:
> > > > GG,
> > > >
> > > > You ask about AlO3.  Do you mean oxidize on
> > > alumimum-
> > > > oxide over Al or Al and oxide combine.  What
> AlO3
> > > > target for metalica?.  Or deposit Al on oxide
> and
> > > then
> > > > a thin layer of LTO and anneal LTO and Al.
> > > >
> > > > Tony
> > > >
> > > >
> > > >
> > > >
> > > > __________________________________
> > > > Do you Yahoo!?
> > > > Yahoo! Mail - You care about security. So do
> we.
> > > > http://promotions.yahoo.com/new_mail
> > > >
> > >
> > >
> > >
> >
> >
> > __________________________________
> > Do you Yahoo!?
> > Take Yahoo! Mail with you! Get it on your mobile
> phone.
> > http://mobile.yahoo.com/maildemo
> 
> --
> Jeannie Perez
> Science and Engineering Technician
> Stanford Nanofabrication Facility
> Stanford University
> Tel: (650) 723-7997
> Fax: (650) 725-6278
> 
> 
> 



		
__________________________________ 
Do you Yahoo!? 
Yahoo! Mail - Helps protect you from nasty viruses. 
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From HotJobs at MicroSurvivor.com  Tue Feb  1 12:23:19 2005
From: HotJobs at MicroSurvivor.com (HotJobs at MicroSurvivor.com)
Date: Tue, 1 Feb 2005 12:23:19 -0800
Subject: Can you Help? Seeking a Consultant in Natural Gas Industry
Message-ID: <200502012023.j11K1tD8019546@localhost.localdomain>


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Principal
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Phone: 650-248-4831
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Enabling Emerging Business
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From edmyers at stanford.edu  Tue Feb  1 17:17:54 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Tue, 01 Feb 2005 17:17:54 -0800
Subject: SpecMat Mtg Minutes, 2/1/05
Message-ID: <6.0.1.1.2.20050201171348.01c47568@edmyers.pobox.stanford.edu>

SpecMat Members,

I've updated the log sheet with the notes I took today.  Please review them 
for correctness and / or dropped items.  Please let me know if there are 
any concerns.

Question, who is responsible for responding to the users and who should be 
on the distribution list (process staff)?

I will respond to Zheng Wang concerning this week's ZnCdS deposition in the 
Metallica.

Ed
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From edmyers at stanford.edu  Wed Feb  2 10:59:16 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Wed, 02 Feb 2005 10:59:16 -0800
Subject: Please schedule a test run of ZnCdS sputtering
In-Reply-To: <000c01c50497$6af4d450$b36b40ab@zwang01>
References: <000c01c50497$6af4d450$b36b40ab@zwang01>
Message-ID: <6.0.1.1.2.20050202104957.01b61320@edmyers.pobox.stanford.edu>

Zheng,

I wanted to update you on the outcome of yesterday's SpecMat meeting.  I 
know you have a Metallica reservation for this Friday and will need a 
response before the official SpecMat notes are published.

You can go ahead with your scheduled deposition.  We are requesting you add 
the TXRF test wafer to this deposition.  I'm sure you remember your group 
committed to provide TXRF testing of potential contamination resulting 
during your deposition.  The hope is the TXRF results will be available 
before your subsequent deposition.

If you have any questions or want assistance in where to place the TXRF 
wafer please contact Jeannie or myself.

Regards,
Ed


At 09:41 AM 1/27/2005, Zheng Wang wrote:
>Dear All,
>
>According to our discussions on ZnCdS RF sputtering, I need to run a 
>test  together with you to check the contamination.
>
>I wish we could schedule it next week. Please let me know how I should 
>proceed.
>
>Thank you.
>-zheng




From mtang at snf.stanford.edu  Wed Feb  2 12:11:34 2005
From: mtang at snf.stanford.edu (Mary Tang)
Date: Wed, 02 Feb 2005 12:11:34 -0800
Subject: I would like to use silicone rubber in the lab
In-Reply-To: <41FEB377.3000101@slac.stanford.edu>
References: <41FEB377.3000101@slac.stanford.edu>
Message-ID: <420133F6.20902@snf.stanford.edu>

Hi Yves --

We discussed your request in yesterday's SpecMat meeting.  I think this 
is generally OK.  But we were also wondering if you had a chance to 
explore some other tried-and-true solutions.  First, there is a nifty 
little holder designed for protection of wafers during KOH etching.  Uli 
has one of these or she can tell you where to purchase one.  Second, 
some people have used silicone elastomer (Sylgard 184/PDMS as opposed to 
the RTV your are using) for KOH etching.  It's a little nicer, because 
you don't have acetic acid in it.  I believe it has been used up to 80C, 
but don't know the results and would suggest you try this on test wafers 
before doing your devices, if you are interested.  The third question 
was which labware you intended to use...  If you are using a general-use 
beaker and a gold-contaminated refluxer, then it's OK, because these are 
not "clean" anyway. 

In summary, please let us know if you have explored or will consider 
these other solutions -- if these don't work for you for some reason, 
please do let us know why, and then we can approve your RTV use (sorry, 
we would rather not approve "just in case" because we would end up with 
too many approved, but not-used, chemicals in the lab.)

Thanks,

Mary


Yves Acremann wrote:

> One of the tricky processing steps is KOH backside etching of wafers 
> with metal structures on the frontside. The main problem is
> the protection of the front side during the etch process. We currently 
> use black wax for that purpose. We had some problems with
> this in the past where the black wax layer failed during very long 
> etches (up to 40 hours for 1.2mm thick Si wafers).
>
> We would like to try to put two wafers front to front and use silicone 
> rubber to seal the edge. In addition, we plan to have black wax on the
> front side.
> We did some tests with silicone rubber and its ability to withstand 
> KOH in our lab at SLAC and this method looks promising.
> We used the following product for our tests (copied from the home 
> depot catalog :-)) ):
>
> "GE 2.8 oz. Clear Silicone Household Glue
> Model GE280 3TG
>
> 100% silicone. Permanently flexible. Adheres to tile, porcelain, 
> glass, fiberglass, marble, wood, steel, aluminum, brick, mortar, 
> concrete, and most plastics. Lifetime satisfaction guarantee. Won't 
> dry out, crack, chip or peel. Easy to use squeeze tube. Can be used as 
> glue, sealant, caulk or gasketing, and for many patch and repair 
> applications around the house and shop."
>
> For our real wafers, we would like to test this method in the 
> cleanroom. As similar materials are likely used during construction of 
> the wet benches, I hope it will be possible to get approval for
> this material. Of corse we only deal with gold contaminated wafers and 
> this is our last processing step (followed by solvent cleaning and 
> sawing the wafer). We also will NOT heat the
> wafer to a temperature higher than 75C (in KOH) and if necessary, we 
> can do the KOH etch in our lab at SLAC.
>
> I did not find the MSDS that corresponds directly to this product, but 
> there is a link containing more information about it:
> http://householdproducts.nlm.nih.gov/cgi-bin/household/brands?tbl=brands&id=7011007 
>
>
> Sincerely
> Yves Acremann
>


-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu



From edmyers at stanford.edu  Thu Feb  3 08:46:15 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Thu, 03 Feb 2005 08:46:15 -0800
Subject: [Fwd: Thin film sputtered aluminum nitride wafer processing]
Message-ID: <6.0.1.1.2.20050203084344.01b5ea58@edmyers.pobox.stanford.edu>

All,

This is Gary's original email concerning AlN processing.  The notes 
indicate we would consider semiclean tools, but not clean 
tools.  Considering the proposed process flow, is there any reason to 
change this stance?

Ed




>-------- Original Message --------
>Subject:        Thin film sputtered aluminum nitride wafer processing
>Date:   Tue, 18 Jan 2005 17:37:05 -0800
>From:   Gary Yama (RTC) <gary.yama at rtc.bosch.com>
>To:     specmat at snf.stanford.edu
>
>
>
>I'm interested in processing sputtered piezoelectric aluminum nitride.
>Film would be deposited at a vendor, photolith, dry etching, wet cleaning, 
>and other processing in CMOS clean equipment.  Assuming the aluminum 
>nitride sputtering tool is CMOS clean, are there any other restrictions on 
>which CMOS clean tool I can use at Stanford?
>
>Are these compatible:
>
>wbdiff
>wbnonmetal
>tylan oxidation
>thermco
>svgcoat, svgdev
>ultratech
>evalign
>drytek2
>p5000
>lampoly
>stsetch
>epi
>gasonics
>
>Thanks - Gary
>
>
>--
>Mary X. Tang, Ph.D.
>Stanford Nanofabrication Facility
>CIS Room 136, Mail Code 4070
>Stanford, CA  94305
>(650)723-9980
>mtang at stanford.edu
>http://snf.stanford.edu




From mdeal at stanford.edu  Thu Feb  3 09:04:12 2005
From: mdeal at stanford.edu (Michael Deal)
Date: Thu, 03 Feb 2005 09:04:12 -0800
Subject: [Fwd: Thin film sputtered aluminum nitride wafer
  processing]
In-Reply-To: <6.0.1.1.2.20050203084344.01b5ea58@edmyers.pobox.stanford.e
 du>
References: <6.0.1.1.2.20050203084344.01b5ea58@edmyers.pobox.stanford.edu>
Message-ID: <6.1.1.1.2.20050203085229.01f36e78@mdeal.pobox.stanford.edu>

Ed,
    I believe his AlN should be classified as semiclean because it is a 
sputtered  material.   While AlN itself is much more stable than Al, etc, 
(much higher melting point), the fact that it is sputtered should preclude 
its use in "clean" tools, such as oxidation furnaces, epi, etc. since 
sputtering  often deposits other metals.   This would be the same for 
sputtered TiN, TaN, and even sputtered Si3N4 and Si.    (In fact, if he is 
having the AlN sputtered at a vendor, we should make sure there is no gold 
or iron contamination.)
                                                 -mike

At 08:46 AM 2/3/2005, Ed Myers wrote:
>All,
>
>This is Gary's original email concerning AlN processing.  The notes 
>indicate we would consider semiclean tools, but not clean 
>tools.  Considering the proposed process flow, is there any reason to 
>change this stance?
>
>Ed
>
>
>
>
>>-------- Original Message --------
>>Subject:        Thin film sputtered aluminum nitride wafer processing
>>Date:   Tue, 18 Jan 2005 17:37:05 -0800
>>From:   Gary Yama (RTC) <gary.yama at rtc.bosch.com>
>>To:     specmat at snf.stanford.edu
>>
>>
>>
>>I'm interested in processing sputtered piezoelectric aluminum nitride.
>>Film would be deposited at a vendor, photolith, dry etching, wet 
>>cleaning, and other processing in CMOS clean equipment.  Assuming the 
>>aluminum nitride sputtering tool is CMOS clean, are there any other 
>>restrictions on which CMOS clean tool I can use at Stanford?
>>
>>Are these compatible:
>>
>>wbdiff
>>wbnonmetal
>>tylan oxidation
>>thermco
>>svgcoat, svgdev
>>ultratech
>>evalign
>>drytek2
>>p5000
>>lampoly
>>stsetch
>>epi
>>gasonics
>>
>>Thanks - Gary
>>
>>
>>--
>>Mary X. Tang, Ph.D.
>>Stanford Nanofabrication Facility
>>CIS Room 136, Mail Code 4070
>>Stanford, CA  94305
>>(650)723-9980
>>mtang at stanford.edu
>>http://snf.stanford.edu
>
>



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74676218139

From mtang at snf.stanford.edu  Fri Feb  4 15:58:56 2005
From: mtang at snf.stanford.edu (Mary Tang)
Date: Fri, 04 Feb 2005 15:58:56 -0800
Subject: I would like to use silicone rubber in the lab
In-Reply-To: <420400EE.1050508@slac.stanford.edu>
References: <41FEB377.3000101@slac.stanford.edu> <420133F6.20902@snf.stanford.edu> <420136D8.6090508@slac.stanford.edu> <42023741.6020702@snf.stanford.edu> <420400EE.1050508@slac.stanford.edu>
Message-ID: <42040C40.1000007@snf.stanford.edu>

Hi Yves and John Paul --

Thanks for giving the Sylgard a try.  The RTV is approved for use in KOH 
etching in gold-contaminated labware at wbgeneral.  Could you apply and 
cure the RTV either outside the cleanroom?  (I'm presuming that it takes 
a day or so to cure and is emitting acetic acid while it does, and that 
you probably don't want to leave this at a bench over night?)

Mary

Yves Acremann wrote:

> Dear Mary
>
> We did some tests with Sylgard 184 from another user and it looks like 
> the RTV we are using in our lab has better adhesion. So please give us 
> official
> approval for this material.
>
> Thanks
> Yves
>
>
> Mary Tang wrote:
>
>> Hi Yves --
>>
>> Sylgard 184 is available from K.R. Anderson for something like 
>> $40/pound (maybe even cheaper than RTV?)  I have some, if you'd like 
>> to try it.  It probably requires more handling (you have to mix two 
>> components, and you might have to de-gas it), but it does not contain 
>> acetic acid (which RTV does -- and I believe that the silicone glue 
>> you were requesting to use was RTV.)  So, if you'd like to give it a 
>> try, you're welcome to this.  If you'd like to stick with your RTV, 
>> that's OK too -- just let us know so we can officially document this 
>> for future reference.
>>
>> Thanks,
>>
>> Mary
>>
>> Yves Acremann wrote:
>>
>>> Dear Mary
>>>
>>> Thanks for your mail. The holder does not work for us as we don't 
>>> have full wafers. I never used Sylgard 184/PDMS, but this may be a 
>>> very interesting material for us.
>>> Is that material in stock / do you know somebody who uses it?
>>> The labware we will use is a general-use beaker and a 
>>> gold-contaminated refluxer (gold contaminated) and our own glassware 
>>> (also only used for gold contaminated
>>> work).
>>>
>>> Regards
>>> Yves
>>>
>>> Mary Tang wrote:
>>>
>>>> Hi Yves --
>>>>
>>>> We discussed your request in yesterday's SpecMat meeting.  I think 
>>>> this is generally OK.  But we were also wondering if you had a 
>>>> chance to explore some other tried-and-true solutions.  First, 
>>>> there is a nifty little holder designed for protection of wafers 
>>>> during KOH etching.  Uli has one of these or she can tell you where 
>>>> to purchase one.  Second, some people have used silicone elastomer 
>>>> (Sylgard 184/PDMS as opposed to the RTV your are using) for KOH 
>>>> etching.  It's a little nicer, because you don't have acetic acid 
>>>> in it.  I believe it has been used up to 80C, but don't know the 
>>>> results and would suggest you try this on test wafers before doing 
>>>> your devices, if you are interested.  The third question was which 
>>>> labware you intended to use...  If you are using a general-use 
>>>> beaker and a gold-contaminated refluxer, then it's OK, because 
>>>> these are not "clean" anyway.
>>>> In summary, please let us know if you have explored or will 
>>>> consider these other solutions -- if these don't work for you for 
>>>> some reason, please do let us know why, and then we can approve 
>>>> your RTV use (sorry, we would rather not approve "just in case" 
>>>> because we would end up with too many approved, but not-used, 
>>>> chemicals in the lab.)
>>>>
>>>> Thanks,
>>>>
>>>> Mary
>>>>
>>>>
>>>> Yves Acremann wrote:
>>>>
>>>>> One of the tricky processing steps is KOH backside etching of 
>>>>> wafers with metal structures on the frontside. The main problem is
>>>>> the protection of the front side during the etch process. We 
>>>>> currently use black wax for that purpose. We had some problems with
>>>>> this in the past where the black wax layer failed during very long 
>>>>> etches (up to 40 hours for 1.2mm thick Si wafers).
>>>>>
>>>>> We would like to try to put two wafers front to front and use 
>>>>> silicone rubber to seal the edge. In addition, we plan to have 
>>>>> black wax on the
>>>>> front side.
>>>>> We did some tests with silicone rubber and its ability to 
>>>>> withstand KOH in our lab at SLAC and this method looks promising.
>>>>> We used the following product for our tests (copied from the home 
>>>>> depot catalog :-)) ):
>>>>>
>>>>> "GE 2.8 oz. Clear Silicone Household Glue
>>>>> Model GE280 3TG
>>>>>
>>>>> 100% silicone. Permanently flexible. Adheres to tile, porcelain, 
>>>>> glass, fiberglass, marble, wood, steel, aluminum, brick, mortar, 
>>>>> concrete, and most plastics. Lifetime satisfaction guarantee. 
>>>>> Won't dry out, crack, chip or peel. Easy to use squeeze tube. Can 
>>>>> be used as glue, sealant, caulk or gasketing, and for many patch 
>>>>> and repair applications around the house and shop."
>>>>>
>>>>> For our real wafers, we would like to test this method in the 
>>>>> cleanroom. As similar materials are likely used during 
>>>>> construction of the wet benches, I hope it will be possible to get 
>>>>> approval for
>>>>> this material. Of corse we only deal with gold contaminated wafers 
>>>>> and this is our last processing step (followed by solvent cleaning 
>>>>> and sawing the wafer). We also will NOT heat the
>>>>> wafer to a temperature higher than 75C (in KOH) and if necessary, 
>>>>> we can do the KOH etch in our lab at SLAC.
>>>>>
>>>>> I did not find the MSDS that corresponds directly to this product, 
>>>>> but there is a link containing more information about it:
>>>>> http://householdproducts.nlm.nih.gov/cgi-bin/household/brands?tbl=brands&id=7011007 
>>>>>
>>>>>
>>>>> Sincerely
>>>>> Yves Acremann
>>>>>
>>>>
>>>>
>>>
>>
>>
>


-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu



From mahnaz at snf.stanford.edu  Fri Feb  4 17:20:46 2005
From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour)
Date: Fri, 04 Feb 2005 17:20:46 -0800
Subject: Material Request
Message-ID: <42041F6E.1010803@snf.stanford.edu>


Hi  Yiching

This is to let you know that developing /etching  PI-5878G is not 
allowed at any of the SVGdev1 or SVGdev2. You may do your processing at 
webmis. in your own  lab ware. Any questions or concerns please contact 
Mary Tang as I will be  on vacation for next few weeks.

mahnaz


From edmyers at stanford.edu  Mon Feb  7 10:06:21 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Mon, 07 Feb 2005 10:06:21 -0800
Subject: Rhett Brewer: Request for Process approval
Message-ID: <6.0.1.1.2.20050207094800.01c0dc28@edmyers.pobox.stanford.edu>

I met with Rhett on Friday and he outlined his process flow.  He is anxious 
to get his pathway cleared so he can resume processing once the ALD system 
is back on line.

1) The wafer will come in to the fab with a third party Pd/Si/O layer.
*Rhett is running TXRF on these wafer to verify the level of cleanliness.

2) Poly Deposition: Wafer will have exposed ALD layer covering Pd/Si/O.
*Where can these wafer be deposited?
*Choices are Tystar or Thermco Poly.
*What is required pre-clean and where can it be done?

3) P5000 ? Poly etch chamber, Al etch chamber:  Poly etch stopping on ALD 
layer.
*Is etching in P5000 allowed?

3) Tylan tube furnace for annealing (whichever is appropriate ? I assume 
tylanfga) at 400C and 600 ? 800 C (this temp not yet determined, but will 
be in that range).
The open areas of Pd/Si/O layer will be removed before anneal.  Anneal may 
be done here, or moved to later in the process.
*Allowed in FGA tube and what is required pre-plean?

4) Tylanpsg for LTO deposition.  400C.  Exposed surfaces will be Si 
substrate and poly
*Allowed in LTO and what is required pre-clean and where?

5) Tylan furnace tube option for LTO densification and possibly #3) 
annealing step.
*Required pre-clean and where?

6) AMT 8110 or Drytek. LTO etch stopping on silicon or poly
*I don't see any concern

7) Resist strip: Gasonics, Piranha and / or PRX
*Need to resolve PRX and Semiclean B compatibility

8) Gryphon or SCT for metallization:
*What and where is required pre-metal clean

9) P500 metal etch:  Stopping on LTO
*I don't see a problem

10) <http://snf.stanford.edu/Equipment/ag4108/ag4108.html>AG4108 Rapid 
Thermal Annealer (Semi-Clean Mode) 600-800C
*Temperature seems too high for aluminum metallization
*What and where is required preclean.


Ed

>From: "Brewer, Rhett T" <rhett.t.brewer at intel.com>
>To: <specmat at snf.stanford.edu>
>
>
>I would like to request formal approval to process a non-standard film in 
>Semi-clean equipment at SNF or determine experiments I need to run to gain 
>approval or find alternative processing solutions.  I would like to begin 
>processing in the next two weeks if at all possible.
>
>The film in question is composed of silicon, oxygen, and palladium (Pd) on 
>a standard 4 inch silicon wafer.  In this film, there is no more than 4 to 
>5 monolayers worth of Pd and it may exist as silicide, metal, or 
>oxide.  This wafer will also have an Al2O3 film on it.
>
>I would like to process this film stack in the following tools at the 
>specified temperatures when applicable:
>
>P5000 ? Poly etch chamber, Al etch chamber
>Tylan tube furnace for annealing (whichever is appropriate ? I assume 
>tylanfga) at 400C and 600 ? 800 C (this temp not yet determined, but will 
>be in that range).
>Tylanpsg for LTO deposition.  400C.
>AMT 8110
>Drytek 100
>Gryphon or STC (Do I have that correct?  The new machine run by Ed Myers) 
>for metal deposition.
><http://snf.stanford.edu/Equipment/ag4108/ag4108.html>AG4108 Rapid Thermal 
>Annealer (Semi-Clean Mode) 600-800C
>
>Additionally, I would like to request the ability to clean the wafers in 
>an appropriate wet bench (wbsilicide?)  The wafers will have to be cleaned 
>at several steps to strip resist and prepare them for entry into these 
>?semi-clean? tools.
>
>Finally, I would like to coat this wafer with poly.  The tystar is the 
>perfect tool (I believe it is both semi-clean and can deposit doped poly), 
>but I understand it is going away.  I would like the ability to put down 
>either n-doped or undoped poly at up to 600C (I expect it will be 
>580C).  I will say that during this process, the silicon, oxygen, 
>palladium film will be completely covered with Al2O3 (>10 nm).  The Al2O3 
>will either be grown at SNF (new ALD chamber) or by an outside vendor.  In 
>either case, before a wafer is introduced into the poly chamber from 
>either the ALD or an outside vendor, I will check a test wafer with TXRF 
>for contaminants.
>
>Eventually, the Al2O3 may be replaced by another high-k (HfO2 maybe).  I 
>just wanted to make you aware of that, but it is not urgent.
>
>I would appreciate a timely response.  I would be happy to meet to answer 
>questions to clarify process and give any information that is appropriate 
>to ensure the compatibility of my process with the needs of the lab.
>
>Thank you.
>
>Rhett Brewer
>Intel Corporation
>work: 408-765-8254
>cell: 408-655-3448
><mailto:rhett.t.brewer at intel.com>rhett.t.brewer at intel.com
>




From cmfaulkn at snf.stanford.edu  Mon Feb  7 15:13:21 2005
From: cmfaulkn at snf.stanford.edu (Carl Faulkner)
Date: Mon, 07 Feb 2005 15:13:21 -0800
Subject: LaB6 in the Innotec
Message-ID: <5.2.1.1.0.20050207150707.00c51890@snf.stanford.edu>

I would like to deposit LaB6 (Lanthanum Hexaboride) in the Innotec possibly 
anneal it in the gold-contaminated Tylan.

I will be using pellets in a graphite liner as the source.  I haven't 
located the vapor pressure of the compound, but it has a melting 
temperature over 2000C and both La and B have better vapor pressures than 
Indium.

It is commonly used in the SEM tips.  It has been investigate by Freescale 
Semiconductor as a possible gate material (IEDM 2004), heated to 800C 
without problem on oxide.

Carl Faulkner
cmfaulkn
650 387-3714



From edmyers at stanford.edu  Mon Feb  7 17:03:18 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Mon, 07 Feb 2005 17:03:18 -0800
Subject: Process Flwow for ALD and Pd/Si/O film request
Message-ID: <6.0.1.1.2.20050207165215.01c55530@edmyers.pobox.stanford.edu>

Here is Rhett's process flow.


>From: "Brewer, Rhett T" <rhett.t.brewer at intel.com>
>To: "Ed Myers" <edmyers at stanford.edu>
>
>
>Ed,
>
>I just finished my excel version of the process flow so I thought I
>would send it anyway.
>
>I think that the RTA step comes after the LTO per your suggestion.
>After metallization we should only have a 400C anneal in tylanfga (I
>believe this is a pretty standard forming gas anneal.)  If the temp is
>too high, I am more than happy to bring it down, but I believe this is a
>standard process.  The only thing non-standard are my films beneath it.
>
>In your previous e-mail you mentioned TXRF.  There are standard
>materials that can be observed in TXRF, but I believe that Au is not one
>of them (I will check into that.)
>
>Certainly because we control the process we can self police and ensure
>no possibility for Au contamination.  Is that sufficient?
>
>Also, when I request TXRF they only do it for the materials I request.
>Do you have a list of specific materials to look for?
>
>Rhett
>
>
>
>-----Original Message-----
>From: Ed Myers [mailto:edmyers at stanford.edu]
>Sent: Monday, February 07, 2005 10:22 AM
>To: Brewer, Rhett T
>Subject: RE: Contamination Experiment and LGA filmsq
>
>Rhett,
>
>I used my notes to send something off to specmat.  I did notice one item
>
>that concerned me.  The RTA you mentioned was after metallization.  The
>temperatures seemed awfully high for aluminum.  You may also want to
>combine your anneal, with the LTO densification.  The wafer will be
>covered
>in LTO and should minimize contamination concern.
>
>Ed
>
>
>At 09:48 AM 2/7/2005, you wrote:
> >Ed,
> >
> >I am making up a process flow for you to send around.  Will be done in
>a
> >few minutes...
> >
> >Rhett
> >
> >-----Original Message-----
> >From: Ed Myers [mailto:edmyers at stanford.edu]
> >Sent: Monday, February 07, 2005 9:48 AM
> >To: Brewer, Rhett T
> >Subject: Re: Contamination Experiment and LGA filmsq
> >
> >Rhett,
> >
> >Outside of getting TXRF measurements on your incoming wafer, I'm not
> >sure
> >what is required.  I need to condense our discussion and forward
> >comments
> >to the SpecMat committee.  I will encourage the committee to give me
> >testing conditions prior to our meeting.  Worst case maybe the meeting
> >will
> >come out with an acceptance criteria that once it is met you can do
>your
> >
> >processing.
> >
> >Regards,
> >Ed
> >
> >
> >At 08:56 AM 2/7/2005, you wrote:
> > >Hi Ed,
> > >I had some issues with my e-mail late last week and some mail got
> > >bounced.  I am resending this important e-mail about the
>contamination
> > >experiment I need to run:
> > >
> > >Thanks for taking time to speak with me this morning.
> > >
> > >I left without a clear experiment to run on my wafers coming into the
> > >fab.  I understand that I need to check the front and backside, but
> >what
> > >is the standard experiment required by Stanford to qualify wafers as
> > >eligible for processing in semi-clean equipment.  I want to make sure
> >that
> > >what I do will satisfy the committee.  Let me know soon so that I can
> >set
> > >it up and get the required analysis done.  Given the typical several
> >day
> > >turn around time for analysis - and my desire to have this data by
>your
> >
> > >Feb. 15th meeting - I need to process my wafers at the beginning of
> >this week.
> > >
> > >Thank you.
> > >
> > >Rhett
> > >
> > >
> > >Additionally, I am looking for a "semi-clean" source for Al2O3
> > >deposition.  I contacted Lance Goddard Associates and they can grow
> >Al2O3,
> > >but I need to know how to determine if they have a qualified
> >"semi-clean"
> > >process.  I am asking basic questions like - does the chamber see Au,
> >Cu,
> > >or Cr.
> > >Do you know of a thin film growth company with "semi-clean" processes
> >that
> > >grow Al2O3 - otherwise, what is the standard procedure for bringing
> >films
> > >from outside vendors in?
> > >
> > >Alternatively - I believe the Balzers was a semi-clean machine and is
> >now
> > >over in physics.  Who would know how to find that machine and if I
> >could
> > >still use it for semi-clean Al2O3 deposition.
> > >
> > >Thanks again.
> > >Rhett
> > >
> > >Rhett Brewer
> > >Intel Corporation
> > >work: 408-765-8254
> > >cell: 408-655-3448
> > ><mailto:rhett.t.brewer at intel.com>rhett.t.brewer at intel.com
> > >
>
>
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From edmyers at stanford.edu  Wed Feb  9 09:43:58 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Wed, 09 Feb 2005 09:43:58 -0800
Subject: Approval E-mails
Message-ID: <6.0.1.1.2.20050209094039.01c67600@edmyers.pobox.stanford.edu>

Committee,

I have not heard any comments concerning the notes from our meeting on 
2/1/05.  As a result I was going to send out confirmation emails to the 
requests approved at the 2/1/05 meeting.  To decrease the number of emails 
you get, I was not going to copy anyone on the email.  If you want to be 
copied, please let me know.

Ed



From amyers at stanford.edu  Thu Feb 10 12:38:54 2005
From: amyers at stanford.edu (Dr. Alan Mark Myers)
Date: Thu, 10 Feb 2005 12:38:54 -0800
Subject: NiV 93%/7% sputter targets in metallica
Message-ID: <1108067934.420bc65eae631@webmail.stanford.edu>


Dear Specmat,
     Today I was busted for using a NiV target in metallica.  The reason Ni
is banned from metallica is that it is a magnectic material and the
magnetic field from the magnetron can not permeate the target to form the
characteristic high density plasma associated with magnetron sputtering. 
When 7% Vanadium is added to the Ni, the magnetism of the target is
quenched and sputtering works fine.  The URL below shows that this is a
standard material for DC magnetron sputtering.
     Please let me know if you need any further infor mation regarding this
subject.

Thanks,

      Alan

http://www.puretechinc.com/data_sheets/nickel_vanadium.htm


From jimkruger at yahoo.com  Fri Feb 11 12:13:49 2005
From: jimkruger at yahoo.com (jim kruger)
Date: Fri, 11 Feb 2005 12:13:49 -0800 (PST)
Subject: Etch to Cu in PQuest ?
Message-ID: <20050211201349.79863.qmail@web40910.mail.yahoo.com>

Jim,

Would it be permitted to etch sputtered SiN (500 A) to
stop on Cu (1000 A, on Thermal SiO2/ Si) in PQuest? 

The etch chemistry is based on the GaAs recipe, 2
mTorr, Ar15, BCl3 5, Cl2 10 with 200 watts uWave and
40 watts RF for 45 or 50 volts DC bias.  

The etch mask is ZEP 520a e-beam resist, with sub
100nm critical dimensions - aiming for very small
pattern transfer.

The open area etching to Cu is only ~ 1% of the ~2x2
cm chip mounted on a 4inch Si carrier wafer with a
high vac compatible electron microscope Carbon
adhesive dot.

Since the area is so small, the bias is so low, and
the Cu would be exposed only in over-etch, little Cu
would be left in the chamber, certainly less than
exposed when others are using approved covered copper
tape in the Pquest.

jimkruger

Mark Wendman


		

__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 


From mcvittie at snf.stanford.edu  Fri Feb 11 14:15:34 2005
From: mcvittie at snf.stanford.edu (Jim McVittie)
Date: Fri, 11 Feb 2005 14:15:34 -0800
Subject: Etch to Cu in PQuest ?
References: <20050211201349.79863.qmail@web40910.mail.yahoo.com>
Message-ID: <420D2E86.F66E351F@snf.stanford.edu>

Jim,

I agree that the amont of Cu etched will be pretty small. I am first
checking with some of the key GaAs users of the tool. If it is ok with
them, I will check with all the PQuest users.

    Jim

jim kruger wrote:

> Jim,
>
> Would it be permitted to etch sputtered SiN (500 A) to
> stop on Cu (1000 A, on Thermal SiO2/ Si) in PQuest?
>
> The etch chemistry is based on the GaAs recipe, 2
> mTorr, Ar15, BCl3 5, Cl2 10 with 200 watts uWave and
> 40 watts RF for 45 or 50 volts DC bias.
>
> The etch mask is ZEP 520a e-beam resist, with sub
> 100nm critical dimensions - aiming for very small
> pattern transfer.
>
> The open area etching to Cu is only ~ 1% of the ~2x2
> cm chip mounted on a 4inch Si carrier wafer with a
> high vac compatible electron microscope Carbon
> adhesive dot.
>
> Since the area is so small, the bias is so low, and
> the Cu would be exposed only in over-etch, little Cu
> would be left in the chamber, certainly less than
> exposed when others are using approved covered copper
> tape in the Pquest.
>
> jimkruger
>
> Mark Wendman
>
>
>
> __________________________________________________
> Do You Yahoo!?
> Tired of spam?  Yahoo! Mail has the best spam protection around
> http://mail.yahoo.com
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From edmyers at stanford.edu  Fri Feb 11 16:11:45 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Fri, 11 Feb 2005 16:11:45 -0800
Subject: Updated log sheet for Tuesday's Meeting
Message-ID: <6.0.1.1.2.20050211154032.01c5b9a0@edmyers.pobox.stanford.edu>

All,

I've updated the SpecMat Log Sheet to cover the items that have come in the 
last couple of weeks.  I hid all of last weeks items where we reached a 
decision.  I also added a lot more comments from the requester.

Regards,
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From mtang at snf.stanford.edu  Mon Feb 14 07:05:18 2005
From: mtang at snf.stanford.edu (Mary Tang)
Date: Mon, 14 Feb 2005 07:05:18 -0800
Subject: [Fwd: Etching Nitride layers - P5000]
Message-ID: <4210BE2E.2040804@snf.stanford.edu>



-------- Original Message --------
Subject: 	Etching Nitride layers - P5000
Date: 	Fri, 11 Feb 2005 13:25:02 -0800
From: 	Ofer Levi <levi at snowmass.stanford.edu>
To: 	Mary Tang <mtang at snf.stanford.edu>
CC: 	Jim McVittie <mcvittie at snf.stanford.edu>, Wonjoo Suh 
<wjsuh at stanford.edu>



Dear Mary,
Following our discussion yesterday, I attach hereby a revised run sheet for 
our sensor wafer that describes the processing I do so far. I can clean the 
sample as needed before coating the sample with E-beam resist and Chrome. 
At the moment I am using Innotec for chrome layer, but if needed I can 
consider doing clean Cr. deposition. After e-beam writing, I remove the 
Chrome layer using the wet Chrome etch, and develop the resist.
I would like to try using the P-5000 etch tool, by mounting my sample onto 
a 4 inch Silicon wafer and etching the Nitride layer.
Thanks,
Ofer


______________________________________________

Ofer Levi,      Ph.D.
Department of Electrical Engineering, Stanford University
CIS-X Rm 310,  Stanford, CA 94305-4075

Phone:                             (650)723-0464 or 725-6907
Fax:                                              (650)723-4659
Adm. Asst.: Gail Chun-Creech                  Ph:  (650)723-0983
E-Mail:                          levi at snow.stanford.edu
Web page:               http://snow.stanford.edu/~levi/
______________________________________________



-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu

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From mtang at snf.stanford.edu  Mon Feb 14 07:05:28 2005
From: mtang at snf.stanford.edu (Mary Tang)
Date: Mon, 14 Feb 2005 07:05:28 -0800
Subject: [Fwd: Re: Etching Nitride layers - P5000]
Message-ID: <4210BE38.6090906@snf.stanford.edu>



-------- Original Message --------
Subject: 	Re: Etching Nitride layers - P5000
Date: 	Fri, 11 Feb 2005 17:35:43 -0800
From: 	Ofer Levi <levi at snowmass.stanford.edu>
To: 	Jim McVittie <mcvittie at snf.stanford.edu>
CC: 	Mary Tang <mtang at snf.stanford.edu>, James Harris 
<harris at snowmass.stanford.edu>, James Conway <jwc at snf.stanford.edu>
References: 	<6.1.2.0.2.20050211103924.0358aeb0 at snow.stanford.edu> 
<420D332A.B1B20 at snf.stanford.edu>



Dear Jim,
I am using a ZEP E-beam resist for my patterns to create the Photonic 
crystal sensor. The thickness of the ZEP resist layer after development 
is  ~ 3000-3500 Ang. over silicon. I am evaluating the resist thickness 
over my Quartz/SiNx samples now, but assume similar thickness.

I talked to Gigi today about etching in Pquest. He suggests that his data 
shows 400/500 A/min. for etching SiNx using the Chlorine based recipe we 
use for GaAs in Pquest. He estimated that the resist etch rate for the ZEP 
resist will be ~ 1000 A/min. This is also what I get for the ZEP resist 
etch rate at Drytek 1, using the Nitride etch recipe (F13/SF6 etch).
It is still ~ 2x better then PMMA for this ZEP resist etch rate but when 
you try to etch the Nitride layer to a depth of 2500 Ang. you need ~ 5 
minutes of etch for this Chlorine based recipe, and by that time the E-beam 
resist will be long gone.

Gigi suggests to keep looking for a solution that will have good etching 
performance with good side wall roughness using Fluorine based chemistry. 
This is why I chose to look into using the P5000 machine for 
etching.  Please also note that before deposition of any materials on my 
sample in the PECVD, I overcoat the walls twice with a 2500 Ang. of Nitride 
(one conditioning coat, and one calibration coat on Silicon wafer) so there 
is not much that can come off the walls onto my sample at that point.
I can also further clean the sample after dicing (I am already using a 
solvent clean, and an Piranha clean to the samples after dicing) to make 
them clean. So, I see no major issue aside from the Chrome layer deposition 
that may prevent my process from etching at the P5000 system. This Chrome 
layer deposition is a common feature for people who use e-beam lithography 
to get better writing performance and image resolution so it is a common 
material in our process. At the moment I do remove this very thin (5 nm) 
layer before etching.

I will be happy to further discuss this issue with you on Monday to look 
into issues with my process, and finding good solutions to them. I will be 
in the clean room most of the day since I write e-beam patterns on the 
Raith from the morning.

Regards,
Ofer



At 02:35 PM 2/11/2005, Jim McVittie wrote:
>Ofer,
>
>There are a number issues with your process which are going to be a 
>problem in getting your samples into
>the P5000. I did not realize it until recently but the GaAs etch process 
>in the PQuest has a high nitride
>etch rate (400 to 500 A/min). I think you should look at doing your etch 
>in the PQuest.
>
>     Jim
>
>Ofer Levi wrote:
>
> > Dear Mary,
> > Following our discussion yesterday, I attach hereby a revised run sheet for
> > our sensor wafer that describes the processing I do so far. I can clean the
> > sample as needed before coating the sample with E-beam resist and Chrome.
> > At the moment I am using Innotec for chrome layer, but if needed I can
> > consider doing clean Cr. deposition. After e-beam writing, I remove the
> > Chrome layer using the wet Chrome etch, and develop the resist.
> > I would like to try using the P-5000 etch tool, by mounting my sample onto
> > a 4 inch Silicon wafer and etching the Nitride layer.
> > Thanks,
> > Ofer
> >
> > ______________________________________________
> >
> > Ofer Levi,      Ph.D.
> > Department of Electrical Engineering, Stanford University
> > CIS-X Rm 310,  Stanford, CA 94305-4075
> >
> > Phone:                             (650)723-0464 or 725-6907
> > Fax:                                              (650)723-4659
> > Adm. Asst.: Gail Chun-Creech                  Ph:  (650)723-0983
> > E-Mail:                          levi at snow.stanford.edu
> > Web page:               http://snow.stanford.edu/~levi/
> > ______________________________________________
> >
> >   ------------------------------------------------------------------------
> >                                                     Name: PC sensor run 
> sheet_February_10_05.doc
> >    PC sensor run sheet_February_10_05.doc           Type: Microsoft 
> Word Document (application/msword)
> >                                                 Encoding: base64
> >                                          Download Status: Not 
> downloaded with message


-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu



From mcvittie at snf.stanford.edu  Mon Feb 14 10:15:13 2005
From: mcvittie at snf.stanford.edu (Jim McVittie)
Date: Mon, 14 Feb 2005 10:15:13 -0800
Subject: NiV 93%/7% sputter targets in metallica
References: <1108067934.420bc65eae631@webmail.stanford.edu>
Message-ID: <4210EAB1.601AD5CB@snf.stanford.edu>

Specmat,

Ni( 9%V) was developed as a barrier between Cu and Al. It is non-magnetic. V
has a low barrier pressure. Its vapor pressure curve lies next to Ti.  V has
the following safety ratings: Health =1, Flammability = 0, Reactivity  = 0. The
numbers for Ni are 3, 0, 0. Note we allow Ni in the SCT. The main downside for
NiV sputtering is that its films tends to have high stress.  This stress can be
reduced with high bias voltages (250V) which we do not have in the Metalica.
Since we have no restrictions concerning stress in the Metalica, it should be
allowed.

    Jim

i

"Dr. Alan Mark Myers" wrote:

> Dear Specmat,
>      Today I was busted for using a NiV target in metallica.  The reason Ni
> is banned from metallica is that it is a magnectic material and the
> magnetic field from the magnetron can not permeate the target to form the
> characteristic high density plasma associated with magnetron sputtering.
> When 7% Vanadium is added to the Ni, the magnetism of the target is
> quenched and sputtering works fine.  The URL below shows that this is a
> standard material for DC magnetron sputtering.
>      Please let me know if you need any further infor mation regarding this
> subject.
>
> Thanks,
>
>       Alan
>
> http://www.puretechinc.com/data_sheets/nickel_vanadium.htm
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From edmyers at stanford.edu  Mon Feb 14 15:38:16 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Mon, 14 Feb 2005 15:38:16 -0800
Subject: Updated Logsheet for 2/15/05 SpecMat Mtg
Message-ID: <6.0.1.1.2.20050214153612.01b6ebb0@edmyers.pobox.stanford.edu>

Attached is the updated log sheet for tomorrows SpecMat meeting.  I've 
hidden all the items that are closed and added more content to the recent 
request.

Regards,
Ed
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From mcvittie at cis.Stanford.EDU  Mon Feb 14 16:56:19 2005
From: mcvittie at cis.Stanford.EDU (Jim McVittie)
Date: Mon, 14 Feb 2005 16:56:19 -0800 (PST)
Subject: Etch to Cu in PQuest ?
In-Reply-To: <20050211201349.79863.qmail@web40910.mail.yahoo.com>
Message-ID: <Pine.LNX.4.44.0502141649080.5620-100000@cis.Stanford.EDU>

Jim,

Here is the reply I got from Gigi about using copper in the PQuest.  

"I remember from Evan's exeperiments that any copper exposed to (Cl) etch
will mess up completely the wafer: that's what happened when even a
little corner of copper taper was left exposed to the plasma. Maybe Evan
can say a bit more about that...
That's all I know about copper"

Since the III-V users use copper tape in the PQuest, copper is not a 
problem to them from a device viewpoint. However, as pointed out above Cu 
can affect GaAs etching. I will contact Evan to see if follow wafers saw 
any affect from the Cu.

	Jim  

On Fri, 11 Feb 2005, jim kruger wrote:

> Jim,
> 
> Would it be permitted to etch sputtered SiN (500 A) to
> stop on Cu (1000 A, on Thermal SiO2/ Si) in PQuest? 
> 
> The etch chemistry is based on the GaAs recipe, 2
> mTorr, Ar15, BCl3 5, Cl2 10 with 200 watts uWave and
> 40 watts RF for 45 or 50 volts DC bias.  
> 
> The etch mask is ZEP 520a e-beam resist, with sub
> 100nm critical dimensions - aiming for very small
> pattern transfer.
> 
> The open area etching to Cu is only ~ 1% of the ~2x2
> cm chip mounted on a 4inch Si carrier wafer with a
> high vac compatible electron microscope Carbon
> adhesive dot.
> 
> Since the area is so small, the bias is so low, and
> the Cu would be exposed only in over-etch, little Cu
> would be left in the chamber, certainly less than
> exposed when others are using approved covered copper
> tape in the Pquest.
> 
> jimkruger
> 
> Mark Wendman
> 
> 
> 		
> 
> __________________________________________________
> Do You Yahoo!?
> Tired of spam?  Yahoo! Mail has the best spam protection around 
> http://mail.yahoo.com 
> 

-- 
--------------------------------------------------------------
Jim McVittie, Ph.D.    			Senior Research Scientist 
Allen Center for Integrated Systems     Electrical Engineering
Stanford University             	jmcvittie at stanford.edu
Rm. 336, 330 Serra Mall			Fax: (650) 723-4659
Stanford, CA 94305-4075			Tel: (650) 725-3640




From rissman at stanford.edu  Tue Feb 15 11:22:25 2005
From: rissman at stanford.edu (Paul Rissman)
Date: Tue, 15 Feb 2005 11:22:25 -0800
Subject: Fwd: 
Message-ID: <5.1.1.5.2.20050215112219.02e23f18@rissman.pobox.stanford.edu>

fyi

>X-Sieve: CMU Sieve 2.2
>X-Sender: mdeal at mdeal.pobox.stanford.edu
>X-Mailer: QUALCOMM Windows Eudora Version 6.1.1.1
>Date: Tue, 15 Feb 2005 09:23:02 -0800
>To: rissman at stanford.edu
>From: Michael Deal <mdeal at stanford.edu>
>Subject:
>
>Paul,
>     I have another meeting so I won't be able to attend the Special 
> Materials meeting today.    -mike




From ankurjn at stanford.edu  Wed Feb 16 09:43:20 2005
From: ankurjn at stanford.edu (Ankur Jain)
Date: Wed, 16 Feb 2005 09:43:20 -0800 (PST)
Subject: Request for a non-standard process
Message-ID: <Pine.LNX.4.44.0502151512500.534-101000@cardinal4.Stanford.EDU>

Hello SpecMat members,
 I would like to make a request for letting me perform a through-wafer
deep reactive ion etch (DRIE) of a Silicon wafer that has a 2 um thin film
of NiTi alloy on the other side of the wafer. I am attaching a powerpoint
file containing the proposed process flow and other information about the
NiTi alloy.
 Please let me know if there is anything else that I need to do and if
there are any other questions.
 I would truly appreciate an expeditious consideration of this request.


regards,

Ankur Jain.
650-799-8986
ankurjn at stanford.edu

*************************************************************************
ANKUR JAIN
Graduate Student
Microscale Heat Transfer Laboratories         Residence:
Room 201, Building 530                        126 Blackwelder Ct, Apt 902
Stanford, CA-94305                            Stanford, CA - 94305
Ph: 650-736-0044                              Cell Ph: 650-799-8986
http://www.stanford.edu/~ankurjn

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From bipin at stanford.edu  Wed Feb 16 13:05:37 2005
From: bipin at stanford.edu (Bipin Rajendran)
Date: Wed, 16 Feb 2005 13:05:37 -0800
Subject: Laser Annealing outside SNF
Message-ID: <028f01c5146b$43d62110$42b20c80@supernova>

Dear Specmat Members,
I am trying to do a modified 410 process, that use laser annealing for activating the source drain regions. I am planning to send my wafers out to a company called AMBP Tech, and below is an email from them telling me about their laser machine. 

My question is this: After I do the annealing, will I be allowed to come back to the lab and continue with the remaining 410 processing ie. Al deposition in gryphon, P5000 etch and FGA anneal? Or will I have to look for alternate set of non-semi-clean equipments to do these?

AMBP Tech's core discipline is in thin film equipment and services and we have used our thin film equipment, located in the same lab as the excimer laser, to deposit various thin films that have been subsequently processed in a clean room to yield working devices.   
Our applications laboratory environment is relatively clean (no industrial processes are ongoing to produce large amounts of particles), but it is not clean room controlled and the processing will be done under normal conditions.  We have not had any customers that have wished to do further processing on the wafers after the laser annealing, only material analysis.  
We have laser processed partially gold coated die previously, the presence of the gold will not affect our ability to process the wafers, though the gold coated part will not absorb many of the 248nm photons and phase transformations of the gold or underlying layers of the gold will have a phase change affected.  

Thanks very much,
Bipin
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From mtang at snf.stanford.edu  Fri Feb 18 08:24:51 2005
From: mtang at snf.stanford.edu (Mary Tang)
Date: Fri, 18 Feb 2005 08:24:51 -0800
Subject: Methyl Sulfonic Acid
In-Reply-To: <6.0.1.1.2.20050218073231.01b56090@edmyers.pobox.stanford.edu>
References: <8A3152FDE2948B42AECCF93BFFA130EC05C326FD@scsmsx401.amr.corp.intel.com> <6.0.1.1.2.20050218073231.01b56090@edmyers.pobox.stanford.edu>
Message-ID: <421616D3.3000108@snf.stanford.edu>

My bad, as I hadn't gotten around to this...  Please keep this in the 
flammables storage cabinet.  I believe that most all the personal 
chemicals stored there in the bin are group L.  Since this is a group D 
material, could you please find a separate container to hold your 
bottle?  This could be a slightly larger plastic box or beaker.  Please 
label the group on this container.

Thanks,

Mary

Ed Myers wrote:

> Alan,
>
> My notes say Mary is looking in to the chemical storage class and it 
> is still an open item.
>
> Ed
>
> At 08:05 PM 2/17/2005, you wrote:
>
>> Ed,
>>         What about the Methyl Sulfonic Acid?
>>
>> Thanks,
>>         Alan
>>
>> -----Original Message-----
>> From: Ed Myers [mailto:edmyers at stanford.edu]
>> Sent: Thursday, February 17, 2005 5:42 PM
>> To: Myers, Alan M
>> Cc: rissman at stanford.edu; jhaydon at snf.stanford.edu; Jeannie Perez
>> Subject: NiV 93%/7% sputter targets in metallica
>>
>> Alan,
>>
>> SpecMat has reviewed your request to (continue) deposit NiV in the
>> Metallica.  Your request has been approved.
>>
>> Regards,
>>
>>
>>  > Dear Specmat,
>>  >      Today I was busted for using a NiV target in metallica.  The
>> reason Ni
>>  > is banned from metallica is that it is a magnectic material and the
>>  > magnetic field from the magnetron can not permeate the target to form
>> the
>>  > characteristic high density plasma associated with magnetron
>> sputtering.
>>  > When 7% Vanadium is added to the Ni, the magnetism of the target is
>>  > quenched and sputtering works fine.  The URL below shows that this is
>> a
>>  > standard material for DC magnetron sputtering.
>>  >      Please let me know if you need any further infor mation
>> regarding this
>>  > subject.
>>  >
>>  > Thanks,
>>  >
>>  >       Alan
>
>


-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu



From ankurjn at stanford.edu  Fri Feb 18 13:51:19 2005
From: ankurjn at stanford.edu (Ankur Jain)
Date: Fri, 18 Feb 2005 13:51:19 -0800 (PST)
Subject: Addendum to my request
Message-ID: <Pine.GSO.4.44.0502181347100.2935-101000@elaine35.Stanford.EDU>

Hello SpecMat members,
 Following discussions with Ed Myers and Jim McVittie, I would like to
propose two alternatives to the way I was planning to doing the DRIE in my
structure. These alternatives are (1) leaving 20-30 um of Si during the
STS etcher and completing the etch in drytek1, or (2) growing a layer of
thermal oxide prior to NiTi sputter and using that as an etch stop for
DRIE.
 I am attaching a powerpoint file explaining these two alternatives. I
will be happy to adopt either of the alternatives if that helps me run the
proposed process.
 Please let me know if there are any questions.


regards,

Ankur.

*************************************************************************
ANKUR JAIN
Graduate Student
Microscale Heat Transfer Laboratories         Residence:
Room 201, Building 530                        126 Blackwelder Ct, Apt 902
Stanford, CA-94305                            Stanford, CA - 94305
Ph: 650-736-0044                              Cell Ph: 650-799-8986
http://www.stanford.edu/~ankurjn
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From akamath at kovio.com  Tue Feb 22 10:05:03 2005
From: akamath at kovio.com (Arvind Kamath)
Date: Tue, 22 Feb 2005 10:05:03 -0800
Subject: Kovio amorphous silicon/polysilicon films
Message-ID: <17AB8DED04002F4E803EE9A3E29ECFA84764F5@koviomail.print-this.com>

Hi,

 

     We would like to use our amorphous/polysilicon  films in the metals
contaminated side of the LTO tube and gold contaminated oxidation
furnace. Attached is supporting documentation showing SIMS of
metal/nonmetal content indicating that there should be little risk to
these tools beyond what they have already been approved for. 

 

     This is a relatively urgent matter for us and a speedy decision
would be appreciated.

 

                                 Regards,

                                                        Arvind Kamath

 

 

 

Kovio amorphous silicon/polysilicon films

 

1.	Arvind Kamath (akamath) 408-738 3360 x321, Pradeep Nataraj
(pnataraj): Monty Cleeves: Kovio Inc.
2.	Material:  Amorphous/Poly silicon derived from liquid (organic)
source at Kovio's fab. Material into SNF will already be in
poly/amorphous form equivalent to LPCVD films.
3.	Vendor /Manufacturer: Kovio Inc. 1145 Sonora Court, Sunnyvale CA
94086 (SNF Lab User)
4.	Reason for Request: Material in film form will be used for
Kovio's proprietary silicon process and needs to be evaluated in
multiple device flows.
5.	Lab Equipment to be used:

Reason for request is to use front end equipment hitherto not used for
our wafers.

	a.	Tylan Gold contaminated Oxidation furnace (wet and dry
oxidation).
	b.	LTO (Metal contaminated side)
	c.	Process Flow: Variants of typical CMOS Process Flow with
metal gate

5.	Amount and form: Thin Film form equivalent to regular LPCVD
silicon. Tens of wafers at a time will be run through any given step.
6.	Storage: Wafers with films will be stored on site (box) or at
Kovio's facility.
7.	Disposal: N/A
8.	Supporting documentation: See attached. Materials analysis shows
that bulk metal levels are not a particular concern and this material
may be used in front end furnaces that allow "metals or gold
contaminated" wafers without any issue.

 

 

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From akamath at kovio.com  Tue Feb 22 10:06:18 2005
From: akamath at kovio.com (Arvind Kamath)
Date: Tue, 22 Feb 2005 10:06:18 -0800
Subject: Kovio Stainless Steel substrate foils.
Message-ID: <17AB8DED04002F4E803EE9A3E29ECFA8476BB2@koviomail.print-this.com>

Hi,

 

     This is the second of our requests. We intend to make devices on
metal substrates of which stainless steel is a prime candidate, having
found early use in the solar and display industries. Please let us know
of your decision and recommendations. We will be happy to make
modifications such that the process capability of SNF is not compromised
in any manner.

 

                 Regards,

                                 Arvind Kamath

 

 

Stainless Steel Foils:

 

1.	Arvind Kamath (akamath) 408-738 3360 x321 :Monty Cleeves: Kovio
Inc.
2.	Material:  Stainless Steel type 304/316 Foil: 2-10 mil thick
(50-250um). Foils will be front and backside covered with thick
(2500Angstrom +) of cured spin on glass or PECVD oxide). Foils will be
polished (mechanically and electrochemically for good adhesion, handling
and printing).
3.	Vendor /Manufacturer: Kovio Inc. 1145 Sonora Court, Sunnyvale CA
94086 (SNF Lab User). Stainless Steel foil is available from multiple
sources. See for example www.goodfellow.com
4.	Reason for Request: Substrate is under evaluation for Kovio's
prototypes and products.
5.	Lab Equipment to be used: 

	a.	All photo/thin film deposition/metrology tools allowing
metal wafers. 
	b.	Tylan Gold contaminated Oxidation furnace 
	c.	LTO (Metal contaminated side)
	d.	Wet benches allowing metals processing.
	e.	Multiple device flows (CMOS variants) will be used.
	f.	If there are multiple users interested at some point :
LPCVD equipment (poly,nitride) that will not be used for clean wafers
and can be dedicated to metals processing.

6.	Amount and form: 4" rounds similar to silicon wafer typically
50-250um thick. 1-20  foils at a time
7.	Storage: Wafers with films will be stored on site (box) or at
Kovio's facility.
8.	Disposal: N/A
9.	Supporting documentation: None at this time. Stainless steel
substrates are used extensively in the R&D community for solar cell and
display fabrication. We expect the passivating oxide to remain intact
and in any case- not to use any critical clean equipment. Foils will be
thick enough for handling rigidity and strength.

 

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From srim at stanford.edu  Tue Feb 22 16:54:19 2005
From: srim at stanford.edu (Seung Bum Rim)
Date: Tue, 22 Feb 2005 16:54:19 -0800
Subject: SU-8
Message-ID: <1109120059.421bd43bc5c34@webmail>

Dear specmat,

I'll try to use SU-8 in litho (coating and developing) processing.
After solidifying it, I'll use it with
metal evaporation(innotec),
dry etch(drytek2 and mrc) processing and
wet etch(wet benches) processing.
Can SU-8 be used in those areas?

Thanks,
Seung Rim
Electrical Engineering
Stanford University


From mtang at snf.stanford.edu  Wed Feb 23 07:31:30 2005
From: mtang at snf.stanford.edu (Mary Tang)
Date: Wed, 23 Feb 2005 07:31:30 -0800
Subject: SU-8
In-Reply-To: <1109120059.421bd43bc5c34@webmail>
References: <1109120059.421bd43bc5c34@webmail>
Message-ID: <421CA1D2.4010909@snf.stanford.edu>

Hi Seung --

Thanks for your request.  We would like a little more information before 
approving your request.  SU-8 is approved for use in the lab.  However, 
it is very strictly regulated where uncured SU-8 may be used, because it 
is extremely difficult to remove, once it is solidified. So we do 
require a few things.

1.  SNF does not purchase and stock SU-8.  However, there is SU-8 on 
hand (from experiments, from labmembers who don't need it anymore.)  You 
can check to see what is on-hand, but you might have to purchase your 
own, if what we have on-hand is not what you are looking for.  If you 
obtain your own, you will have to register your chemical bottle -- 
Mahnaz & Ed  have barcoards and labels.

2. SU-8 may be applied only at the Headway coater.  Only the designated 
cassette and cassette box may be used.  Even if you are already 
qualified on the Headway, you must be retrained to use SU-8.  Please 
make an appointment to train with Mahnaz or James.

3.  Solid SU-8 may be used in the aligners (karlsuss, evalign, etc.)  It 
must be developed manually at the litho wet bench next to the Headway 
coater.

4.  Solid SU-8 may be used in the drytek2 and the mrc.  However, please 
remember that drytek2 is semiclean, so if your process flow include 
innotec before etching, you should not use drytek2.  The mrc is 
gold-compatible, so is OK following innotec.

5.  Which wet benches do you plan to use?  SU-8 CANNOT be processed at 
any of the standard wet benches (wbnonmetal, wbnitride, wbmetal, wbdiff, 
wbsilicide).  SU-8 material CAN only be processed at the manual wet 
benches (wbgeneral, wbgaas, wbsolvent, lithosolv, litho wet benches.)

Please let us know what you plan to do and feel free to ask us any 
questions about processing SU-8.

Thanks,


Mary

Seung Bum Rim wrote:

>Dear specmat,
>
>I'll try to use SU-8 in litho (coating and developing) processing.
>After solidifying it, I'll use it with
>metal evaporation(innotec),
>dry etch(drytek2 and mrc) processing and
>wet etch(wet benches) processing.
>Can SU-8 be used in those areas?
>
>Thanks,
>Seung Rim
>Electrical Engineering
>Stanford University
>  
>


-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu



From gloriamt at stanford.edu  Sun Feb 27 14:52:06 2005
From: gloriamt at stanford.edu (Gloria Man Ting Wong)
Date: Sun, 27 Feb 2005 14:52:06 -0800
Subject: Cleaning for tylanfga
Message-ID: <1109544726.42224f1610cb4@webmail.stanford.edu>

Hi,

What is the proper procedure for cleaning before tylanfga?  My films have Nb
and W on them (and have only been through semi-clean equipment), and I am
not sure if they have been approved for cleaning in wbmetal.

Also, for wafers that must leave the cleanroom for electrical measurements,
can they be returned to the cleanroom for processing in tylanfga?

Thanks,
Gloria


From wangz at stanford.edu  Mon Feb 28 11:56:17 2005
From: wangz at stanford.edu (Zheng Wang)
Date: Mon, 28 Feb 2005 11:56:17 -0800
Subject: RF sputtering of ZnCdS in Metalica
Message-ID: <001e01c51dcf$9143c2a0$b36b40ab@zwang01>

Dear Specmat Committee,

To minimize the cross contamination of ZnCdS sputtering to the Metalica system, we have tried the TXRF analysis once by hanging two pieces of wafers in-situ. These two pieces of wafers were from Jeanine. One had gold stripes from Innotec, the other was taken from the stock room.
The TXRF result gives a wide range of contaminations, which is more than we expected. After consulting with Jim McVittie, we think it might be worth to re-test the system with a pre-diffusion level cleaned wafer NOT a dirty wafer or a wafer directly from the stock room. 

At the same time we are making efforts to surround our dedicated wafer holder with a aluminum skirt and reconfigure the plasma igniter.

I tentatively make a reservation on Metalica this Friday 9-1 pm.

Please give me the permission. 

Thanks.

-zheng
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From xfan at chemistry.ucsc.edu  Mon Feb 28 15:29:31 2005
From: xfan at chemistry.ucsc.edu (Xiaojuan Fan)
Date: Mon, 28 Feb 2005 15:29:31 -0800
Subject: New chemical
Message-ID: <MLEAJPIBDGIDCFNBFOIHGEIHCBAA.xfan@chemistry.ucsc.edu>


Dear Safety Staff,

I am new labmember, Xiaojuan (Judy) Fan, I will bring a new chemical
1,10-decanedithiol, 10 ml, liquid, in small bottle, its MSDS is attached. I
will use it to make 10mM solution in Ethanol in a glass beaker, then put
gold film silicon wafer into the solution over night for growing monolayer
on gold.  Please advise if the chemical can be used in the lab? How to carry
it into the lab? Where to store it?

Best regards,
Judy
________________________
Dr. Xiaojuan (Judy) Fan
Research Associate
Department of Chemistry & Biochemistry
University of California, Santa Cruz
Santa Cruz, CA 95064
Tel: (831) 459-4225 (O)
Fax: (831) 459- 2935




From edmyers at stanford.edu  Mon Feb 28 16:33:29 2005
From: edmyers at stanford.edu (Ed Myers)
Date: Mon, 28 Feb 2005 16:33:29 -0800
Subject: A couple of quick SpecMat Requests
Message-ID: <6.0.1.1.2.20050228162531.01c95af8@edmyers.pobox.stanford.edu>

All,

There are two users who are anxious for a SpecMat decision.  They are 
fairly simple questions, which I was hoping we could resolved through email 
before next week's meeting.  Please comment on both requests.

1) Rhett Brewer:
A)  Can I use rtaag to do a ~250C O2 anneal of my Pd, Si, O film with ~3-4 
monlayers worth of carbon.
B)  Want to verify that my film stack: si(100)/Si,Pd,O/200A Al2O3/5000A 
P-doped poly Si is allowed in the RTA 4108.  Want to do a 2 min., 650C N2 
or O2 anneal.

Ed's Comments:
A) Should be fine in RTAag since it runs under thermal couple control.
B) The Si-Pd-O film will be buried under our polysilicon film.   This 
should be fine as long as he undergoes the standard pre-RTA clean and use 
the silicide tray.


2) Carl Faulkner
We would like to use Tylan4 - not for forming gas, but for 800C - 1000C 
anneals in nitrogen.  The samples would be Ti- or W-capped LaB6 on 
otherwise standard Si/oxide/nitride substrates.  LaB6 has a melting point > 
2000C.

Ed's Comments:
I don't see a problem with this request as long as there is an appropriate 
clean.  Tylan4 is no longer considered a clean furnace.

Regards,
Ed