SpecMat Update and Items

Ed Myers edmyers at stanford.edu
Tue Nov 1 16:49:01 PST 2005

SpecMat Members,

My poor time management has resulted in me not sending out the "Official" 
email to our requester.  There are a couple of controversial items I want 
to pass on to the committee before the emails.  Nancy was a big help in 
defining the wet bench solutions.  Please look over the items and 
comments.  If there is a quorum, maybe someone (Mary?) could notify the users.

>1)  H2O/HCl/H2O2 and 50:1 HF pots for Ge cleaning: Abhijit Pethe
>     H2O/HCl/H2O2 etching can be done in the silicide 5:1:1 pot as long as 
> it's at room temperature.
>     50:1 HF, assign the 6:1 BOE pot to Ge.

2) SC1 (NH4/H2O2/H2O) and SC2 (HCl/H2O2/H2O) on Si3N4 film from outside CIS 
prior to Poly deposition: Jun-Fei Zheng
         A single pot solution: SC1 and SC2 can be ran through the 
H2O/HCl/H2O2 pot?  It is set for 70C and the SC2 would act as a clean for 
the SC1.  The second bath would need to be prepared as the wafers are in 
the dumprinser.
         TXRF data is suppose to be supplied with the wafer.  Running the 
process depends on having a clean wafer.

3) McIntyre ALD Hf02 processing in Semiclean Tools: Ching-Huang
         TXRF data show the wafers to have an Fe contamination level of 
1.2E-12 cm-2.  This level of contamination puts the substrate in to our 
"Gold Contaminated" equipment set.
         I believe we need to push back.  The users should put in an effort 
to clean up their system before we accept this level of contamination  in 
to our Semiclean group.  This also provides a learning opportunity which 
Prof. Nishi says we owe to our students.

4) What is our fga2 clean?  At least PRX127 or a solvent clean sequence?
         PRS1000 at Wbgenral and or Matrix asher.

5) NH3 Anneal in tylanfga: Chi On
         PRS1000 @ 40C preclean, Push and Pull in Nitrogen and look into 
tube clean after running.

6) Clean processing of Si wafer, that has Al metal wires, covered fully 
with thick LTO, which is CMPed at Cornell. Onto this wafer, I will bond a 
thin back ground an SOI wafer, thus creating my 'second device layer'.
         The back grinding will occur at Aptek Industries.  I've requested 
TXRF data to verify the cleanliness of the wafer.  Does anyone know of the 
cleanliness of Aptek?  I think most are OK with running the CMP'd wafer 
from Cornell.


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