Request for allowing poly and annealing process of wafers with CMOS compatible Si3N4 from outside Stanford CIS

Zheng, Jun F jun.f.zheng at
Tue Nov 15 16:56:10 PST 2005

Dear SpecMat Members and all,

Since I was informed verbally about the utilizing silicide wetbench for
the wafer clean in the past two days, I have sent an urgent request per
Ed's suggestion to allow me to do clean in wbdiff instead of wbsilicide
(see attached). I was concerned because my wafers, which are considered
clean as stated by Ed's email below for the clean equipment set, can be
reversed contaminated if I use silicide wetbench clean.

After I am trained this afternoon by gladys on both wbdiff and
wbsilicide, I more prefer to use the wbdiff, just because I am not
comfortable that the silicide wetbench is potentially metal
contamination at 10x higher than that of wbdiff, according to Ed.

I have spoken to Jim, Mary and Ed continuously in the past few days.
Jim's opinion is to go by TXRF. Mary's opinion is that as long as I can
do the wet clean in wbdiff at non-regular hours to avoid impact of the
chemical change to other people, I can do wbdiff. Ed seems to open but
like to go by the committee members/ 

How is the possibility of followings: 

I will clean my wafer at earlier morning or evening in wbdiff to make
wafer clean first. I will then dump/change the chemical so everything
will be fresh for next user. This will minimize not only time constrains
for others and also less concern on contamination.

Then I will treat my wafer as clean and then clean the wafer again in
wbdiff right before going into furnace.

Please let me know as I was originally planning to do diffusion
annealing at 2:30pm and then poly after annealing tomorrow.



-----Original Message-----
From: Ed Myers [mailto:edmyers at] 
Sent: Tuesday, November 15, 2005 3:22 PM
To: Zheng, Jun F
Cc: rissman at; maurice at;
gladys at; uli Thumser
Subject: Re: Request for allowing poly and annealing process of wafers
with CMOS compatible Si3N4 from outside Stanford CIS


I know you are aware of SpecMat's decision, but I do need to send out an

official statement.  Thank you for suppling the VPD data for your 
wafer.  The contamination levels are within the limits set for our clean

equipment set.

SpecMat has reviewed your request and provides the following process 

The SC!/SC2 cleans can be done at wet bench silicide in the 5:1:1 pot 
(which is set for 70C), or in dedicated clean personal beakers.  We ask 
that you use the 5:1:1 pot for both of your clean steps.  You will need
change the chemistries while your sample is going through the dump

The wafer can be ran through the Thermco furnace for anneal and poly 
deposition, but you must meet the 1 hour window between finishing the
and loading the wafer in to the furnace.  You may move the wafer from
furnace tube to the next, within 1 hour without doing any additional


At 09:47 AM 9/30/2005, you wrote:
>Sept. 30, 2005
>To: Member of Special Materials Committee
>From: Jun-Fei Zheng
>Sub: Processing of Poly deposition on wafers received Si3N4 film from 
>outside CIS
>We are evaluating Jet Vapor Deposited (JVD) Si3N4 film at Yale
>for certain applications. The process is CMOS compatible in a custom
>machine and wafers of 8" and 12" has been cross processed for CMOS 
>application with several major semiconductor companies, including 
>Intel.  To illustared the details, the materials involved in the
>are quartz, Teflon, and CMOS quality gas sources. JVD Si3N4 was process
>mixture of SiH4 and Nitrogen gas in remote plasma through a quartz
>nozzle with He gas as carrying gas in an outer nozzle. The process is 
>conducted at room temperature, which future reduce risk of high 
>temperature diffusion induced contamination. We have tested the film 
>contamination level by VPD (vapor phase decomposition) and all the 
>metallic contents are below detecting limit or less than 10e^10/cm2,
>criteria that we take such wafers into diffusion and poly furnace at
>development line for further process without concerning the
>based on the contamination test results. We only processed the wafer 
>through SC1 and SC2 bath as precaution measure before inserted into
Intel line.
>We are requesting to allow the same materials to be processed in CIS
>in-situ poly deposition and annealing furnace. We want to run this at
>because we need in-situ poly deposition capability. In order to fit the
>tube or 4" tube, the 8" wafer has been notch cut and cleaned into half,

>with the short dimension of 4", so that can be inserted into 6" or 4"
>We sincerely hope our request can be granted. We also wanted to avoid 
>H2SO4:H2O2 process as our wafer has never been through Lithographic 
>process and this is what the H2SO4:H2O2 mainly for but H2SO4:H2O2
>might destroy the gate quality Si3N4. We also do not see the need for
>HF dip, which is used for clear oxide formed on Silicon during
>process. We believe SC1 and SC2 in combination would be able to address

>potential contamination during wafer handling and shipping.
>If you have any suggestion and question, please reply to my e-mail or 
>contact me at (408)921-8763 (cell).
>Jun-Fei Zheng
>Senior Staff Scientist
>Intel Corporation
>Strategic Technology Group
>3065 Bower Ave
>Santa Clara, CA 95052

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Subject: FW: Urgent, where to clean the wafer => RE: Request for allowing  poly and annealing  process of  wafers with CMOS compatible Si3N4 from  outside Stanford  CIS
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