SpecMat Approval: Poly and annealing process of wafers with CMOS compatible Si3N4 from outside Stanford CIS

Ed Myers edmyers at stanford.edu
Wed Nov 16 10:31:17 PST 2005


Jun-Fei,

SpecMat has reviewed your recent request and it has been approved within 
the following guidelines.

1.  Cleaning of your wafers and decontamination of the diffusion 5:1:1 tank 
must at time which is not busy in the lab.  I reviewed the history of the 
diffusion wet bench and the available times are:

weekdays: 12 midnight to 8:00am
weekends: 6 pm to 10 am.

All of his processing should be completed during this time, including 
decontamination of the tank after your use.

2.  Reserve the bench for the time required.

3.  Send a broadcast note to wbdiff at snf.stanford.edu, notifying everyone 
that you plan to use the bench and have reserved it, so people can plan 
around this or adjust their plans accordingly.

4.  Limit the SC1 and SC2 chemistries to the 5:1:1 at the 70C operating 
temperature, just as we were going to do in the silicide wet bench.
Post a large, note above the 5:1:1 hot pot, so no one inadvertently uses it.

5.  Approved Process Sequence for the diffusion wet bench 5:1:1 pot.
Drain, rinse 5:1:1 pot
Pour SC1 chemistry
Process wafers
Drain, rinse 5:1:1 pot
Pour SC2 chemistry
Process Wafers
Drain, rinse 5:1:1 pot
Decontaminate 5:1:1 pot (Twenty minutes of self-heating solution of 1:1:1 
H2O:H2O2:HCl)
Drain, Rinse 5:1:1 pot

6.  Pre-clean time limits
Either the wafers have to be moved between the furnaces within 1 hour or 
the above cleaning sequence needs to be repeated (during the off hours).

Regards,


At 04:56 PM 11/15/2005, Zheng, Jun F wrote:
>Dear SpecMat Members and all,
>
>Since I was informed verbally about the utilizing silicide wetbench for
>the wafer clean in the past two days, I have sent an urgent request per
>Ed's suggestion to allow me to do clean in wbdiff instead of wbsilicide
>(see attached). I was concerned because my wafers, which are considered
>clean as stated by Ed's email below for the clean equipment set, can be
>reversed contaminated if I use silicide wetbench clean.
>
>After I am trained this afternoon by gladys on both wbdiff and
>wbsilicide, I more prefer to use the wbdiff, just because I am not
>comfortable that the silicide wetbench is potentially metal
>contamination at 10x higher than that of wbdiff, according to Ed.
>
>I have spoken to Jim, Mary and Ed continuously in the past few days.
>Jim's opinion is to go by TXRF. Mary's opinion is that as long as I can
>do the wet clean in wbdiff at non-regular hours to avoid impact of the
>chemical change to other people, I can do wbdiff. Ed seems to open but
>like to go by the committee members/
>
>How is the possibility of followings:
>
>I will clean my wafer at earlier morning or evening in wbdiff to make
>wafer clean first. I will then dump/change the chemical so everything
>will be fresh for next user. This will minimize not only time constrains
>for others and also less concern on contamination.
>
>Then I will treat my wafer as clean and then clean the wafer again in
>wbdiff right before going into furnace.
>
>Please let me know as I was originally planning to do diffusion
>annealing at 2:30pm and then poly after annealing tomorrow.
>
>Regards,
>
>Jun-Fei
>
>
>-----Original Message-----
>From: Ed Myers [mailto:edmyers at stanford.edu]
>Sent: Tuesday, November 15, 2005 3:22 PM
>To: Zheng, Jun F
>Cc: rissman at stanford.edu; maurice at snf.stanford.edu;
>gladys at snf.stanford.edu; uli Thumser
>Subject: Re: Request for allowing poly and annealing process of wafers
>with CMOS compatible Si3N4 from outside Stanford CIS
>
>Jun-Fei,
>
>I know you are aware of SpecMat's decision, but I do need to send out an
>
>official statement.  Thank you for suppling the VPD data for your
>wafer.  The contamination levels are within the limits set for our clean
>
>equipment set.
>
>SpecMat has reviewed your request and provides the following process
>recommendations.
>
>The SC!/SC2 cleans can be done at wet bench silicide in the 5:1:1 pot
>(which is set for 70C), or in dedicated clean personal beakers.  We ask
>that you use the 5:1:1 pot for both of your clean steps.  You will need
>to
>change the chemistries while your sample is going through the dump
>rinser.
>
>The wafer can be ran through the Thermco furnace for anneal and poly
>deposition, but you must meet the 1 hour window between finishing the
>clean
>and loading the wafer in to the furnace.  You may move the wafer from
>one
>furnace tube to the next, within 1 hour without doing any additional
>cleans.
>
>Regards,
>
>
>At 09:47 AM 9/30/2005, you wrote:
> >Sept. 30, 2005
> >
> >To: Member of Special Materials Committee
> >
> >From: Jun-Fei Zheng
> >
> >Sub: Processing of Poly deposition on wafers received Si3N4 film from
> >outside CIS
> >
> >We are evaluating Jet Vapor Deposited (JVD) Si3N4 film at Yale
>University
> >for certain applications. The process is CMOS compatible in a custom
>built
> >machine and wafers of 8" and 12" has been cross processed for CMOS
> >application with several major semiconductor companies, including
> >Intel.  To illustared the details, the materials involved in the
>process
> >are quartz, Teflon, and CMOS quality gas sources. JVD Si3N4 was process
>by
> >mixture of SiH4 and Nitrogen gas in remote plasma through a quartz
>inner
> >nozzle with He gas as carrying gas in an outer nozzle. The process is
> >conducted at room temperature, which future reduce risk of high
> >temperature diffusion induced contamination. We have tested the film
> >contamination level by VPD (vapor phase decomposition) and all the
> >metallic contents are below detecting limit or less than 10e^10/cm2,
>the
> >criteria that we take such wafers into diffusion and poly furnace at
>Intel
> >development line for further process without concerning the
>contamination
> >based on the contamination test results. We only processed the wafer
> >through SC1 and SC2 bath as precaution measure before inserted into
>Intel line.
> >
> >We are requesting to allow the same materials to be processed in CIS
>for
> >in-situ poly deposition and annealing furnace. We want to run this at
>CIS
> >because we need in-situ poly deposition capability. In order to fit the
>6"
> >tube or 4" tube, the 8" wafer has been notch cut and cleaned into half,
>
> >with the short dimension of 4", so that can be inserted into 6" or 4"
>tube.
> >
> >We sincerely hope our request can be granted. We also wanted to avoid
> >H2SO4:H2O2 process as our wafer has never been through Lithographic
> >process and this is what the H2SO4:H2O2 mainly for but H2SO4:H2O2
>process
> >might destroy the gate quality Si3N4. We also do not see the need for
>50:1
> >HF dip, which is used for clear oxide formed on Silicon during
>H2SO4:H2O2
> >process. We believe SC1 and SC2 in combination would be able to address
>
> >potential contamination during wafer handling and shipping.
> >
> >If you have any suggestion and question, please reply to my e-mail or
> >contact me at (408)921-8763 (cell).
> >
> >Sincerely,
> >
> >Jun-Fei Zheng
> >Senior Staff Scientist
> >Intel Corporation
> >Strategic Technology Group
> >SC1-05
> >3065 Bower Ave
> >Santa Clara, CA 95052
> >
> >
>
>
>
>
>X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0
>Content-class: urn:content-classes:message
>MIME-Version: 1.0
>Content-Type: multipart/mixed;
>         boundary="----_=_NextPart_002_01C5E952.C7E21600"
>Subject: FW: Urgent, where to clean the wafer => RE: Request for 
>allowing  poly and annealing  process of  wafers with CMOS compatible 
>Si3N4 from  outside Stanford  CIS
>Date: Mon, 14 Nov 2005 11:37:18 -0800
>X-MS-Has-Attach: yes
>X-MS-TNEF-Correlator:
>Thread-Topic: Urgent, where to clean the wafer => RE: Request for 
>allowing  poly and annealing  process of  wafers with CMOS compatible 
>Si3N4 from  outside Stanford  CIS
>Thread-Index: AcXTPSk5dkHCC/WASqiCOHylUsr+sAV7mZAQAAmzANA=
>X-Priority: 1
>Priority: Urgent
>Importance: high
>From: "Zheng, Jun F" <jun.f.zheng at intel.com>
>To: <mcvittie at cis.stanford.edu>
>
>Jim,
>
>Here is the TXRF result. This is from the same wafer, just one of the
>1/4 (quarter wafer). I plan to process the two of the 1/4 quarter wafers
>at Stanford SNF. Like I said, I need the split on the same film and that
>is why I have do it at Stanford (full 8" I do that at Intel).
>
>Best Regards,
>
>Let me know if you have any question. My cell phone is (408)921-8763 so
>you may phone me for quick discussion as well.
>
>Jun-Fei
>
>-----Original Message-----
>From: Zheng, Jun F
>Sent: Monday, November 14, 2005 7:31 AM
>To: 'specmat at snf.stanford.edu'
>Cc: 'Ed Myers'; 'jun-fei.zheng at yale.edu'; 'mtang at stanford.edu'
>Subject: Urgent, where to clean the wafer => RE: Request for allowing
>poly and annealing process of wafers with CMOS compatible Si3N4 from
>outside Stanford CIS
>Importance: High
>
>Dear Member of Specmat,
>
>My request for processing CMOS compatible Si3N4 film has been approved
>according Ed verbally (Ed is too busy to send to me an e-mail). This is
>after TXRF data was provided. The TXRF data shows that the wafer is
>clean.
>
>While everything have been arranged to run the wafers this Wednesday, in
>my discussion with Ed regarding where and how to do the SC1/SC2 clean. I
>was informed by Ed that I was suggested to clean the wafer in SC1/SC2
>chemical in a SC2 pot in wbsilicide. I am concerned because I should
>have been allowed to do wbdiffusion based on TXRF data.
>
>I am following Ed's suggestion to make this urgent request that to allow
>my wafer to be processed in wbdiff.
>
>My wafers are CMOS compatible and the work requires extremely care on
>metallic contamination. Going through wetsilicide that has potential
>metallic contamination issue is not some things I had prepared and
>perhaps will defeat my purpose of experiments.
>
>I can understand your concern of wafer from outside sources. However, we
>should make the decision based on the provided TXRF data. Also, as
>references, similar wafers have been run through Intel, Motorola, SONY,
>and TSMC diffusion wetbench and diffusion furnaces fab many times
>following the same protocol of SC1/SC2 chemical clean. I mention this
>just because the wafers from the source at Yale are made to be
>compatible with frontend non metal diffusion.
>
>Could you please consider this again and allow me to use Wbdiff to clean
>the wafer?
>
>I am set to run the wafer this Wed. afternoon and I will be trained by
>Mary Tuesday afternoon for wet bench clean. Your attention to this
>matter and earlier decision would allow me to go forward to process my
>wafer as originally intended. I am traveling from east coast (Yale
>University) and I am only here this week+ one day next Monday.
>
>Best Regards and look forward to hearing from you. You may call me by
>Cell phone (408)921-8763 if you have more questions than what I stated
>in the e-mails.
>
>Thanks for your attention and consideration.
>
>Jun-Fei Zheng
>Senior Staff Scientist
>Intel Corporation
>Strategic Technology Group
>SC1-05
>3065 Bower Ave
>Santa Clara, CA 95052
>
>Cell (408)921-8763
>
>
>
>afternoon through annealing furnace and LPCVD poly in thermoco to, be
>trained by Mary for SC1/SC2 in weddiff and websilicide tomorrow
>
>-----Original Message-----
>From: Ed Myers [mailto:edmyers at stanford.edu]
>Sent: Monday, October 17, 2005 10:06 AM
>To: Zheng, Jun F
>Subject: Re: Status?=> RE: When will be the meeting?=>RE: Wafer size fit
>to 6" furnance => RE: Request for allowing poly and annealing process of
>wafers with CMOS compatible Si3N4 from outside Stanford CIS
>
>Jun-Fei,
>
>Sorry about the delay, but I was unexpectedly out of the office on
>Friday.
>
>In general it looks like your request will be approved.  We are looking
>at
>where you can do your wafer cleaning.  Best case, we will allocate a hot
>
>pot, worst case it will have to be done in your own, clean beakers.
>
>Remember, this is all contingent on you providing TXRF data which shows
>the
>contamination levels in your samples compatible with our limits.
>
>Regards,
>Ed
>
>
>At 09:30 AM 10/14/2005, you wrote:
> >Ed,
> >
> >I just left a message on your voice mail. Could you please let me know
> >the status of the review?
> >
> >I may also be reached by (408)921-8763, which is my cell phone.
> >
> >Thanks,
> >
> >Jun-Fei
> >
> >-----Original Message-----
> >From: Ed Myers [mailto:edmyers at stanford.edu]
> >Sent: Monday, October 10, 2005 4:03 PM
> >To: Zheng, Jun F
> >Subject: Re: When will be the meeting?=>RE: Wafer size fit to 6"
> >furnance => RE: Request for allowing poly and annealing process of
> >wafers with CMOS compatible Si3N4 from outside Stanford CIS
> >
> >Jun-Fei,
> >
> >The normal meeting time is this Tuesday afternoon.  Many of the members
> >have conflicts, so we will attempt to resolve the SpecMat request by
> >email.
> >
> >Ed
> >
> >At 08:17 AM 10/10/2005, you wrote:
> > >Ed,
> > >
> > >When will be the meeting?
> > >
> > >Thanks,
> > >
> > >Jun-Fei
> > >
> > >-----Original Message-----
> > >From: Ed Myers [mailto:edmyers at stanford.edu]
> > >Sent: Friday, October 07, 2005 11:17 AM
> > >To: Zheng, Jun F
> > >Cc: latta at snf.stanford.edu
> > >Subject: Re: Wafer size fit to 6" furnance => RE: Request for
>allowing
> > >poly and annealing process of wafers with CMOS compatible Si3N4 from
> > >outside Stanford CIS
> > >
> > >Jun-Fei,
> > >
> > >Your request will be considered at the next SpecMat meeting, which is
> > >scheduled for next week.
> > >
> > >Regards
> > >
> > >
> > >At 02:47 PM 10/6/2005, you wrote:
> > > >Nancy,
> > > >
> > > >Thanks for checking if an half of 8" wafer (4" wide) can be layer
> >flat
> > >on
> > > >a boat inside a 6" tube. Assuming the boat is the same for poly and
> > > >annealing (oxidation furnace).
> > > >
> > > >Ed,
> > > >
> > > >I am back to east coast, we will certainly do TXRF on a pieces of
>the
> > >8"
> > > >wafer to demonstrate that the wafer is free from metallic
> >contamination
> > >
> > > >(below certain level that CMOS line would accept).
> > > >
> > > >Have you reviewed my request as outlined below?
> > > >
> > > >Jun-Fei
> > > >
> > > >
> > > >----------
> > > >From: Zheng, Jun F
> > > >Sent: Thursday, October 06, 2005 2:44 PM
> > > >To: 'latta at snf.stanford.edu'; 'emyers at snf.stanford.edu'
> > > >Subject: FW: Request for allowing poly and annealing process of
> >wafers
> > > >with CMOS compatible Si3N4 from outside Stanford CIS
> > > >
> > > >
> > > >
> > > >
> > > >----------
> > > >From: Zheng, Jun F
> > > >Sent: Friday, September 30, 2005 10:47 AM
> > > >To: 'SpecMat at snf.stanford.edu'
> > > >Cc: Chui, Chi On; Zheng, Jun F
> > > >Subject: Request for allowing poly and annealing process of wafers
> >with
> > >
> > > >CMOS compatible Si3N4 from outside Stanford CIS
> > > >
> > > >Sept. 30, 2005
> > > >
> > > >To: Member of Special Materials Committee
> > > >
> > > >From: Jun-Fei Zheng
> > > >
> > > >Sub: Processing of Poly deposition on wafers received Si3N4 film
>from
> > > >outside CIS
> > > >
> > > >We are evaluating Jet Vapor Deposited (JVD) Si3N4 film at Yale
> > >University
> > > >for certain applications. The process is CMOS compatible in a
>custom
> > >built
> > > >machine and wafers of 8" and 12" has been cross processed for CMOS
> > > >application with several major semiconductor companies, including
> > > >Intel.  To illustared the details, the materials involved in the
> > >process
> > > >are quartz, Teflon, and CMOS quality gas sources. JVD Si3N4 was
> >process
> > >by
> > > >mixture of SiH4 and Nitrogen gas in remote plasma through a quartz
> > >inner
> > > >nozzle with He gas as carrying gas in an outer nozzle. The process
>is
> > > >conducted at room temperature, which future reduce risk of high
> > > >temperature diffusion induced contamination. We have tested the
>film
> > > >contamination level by VPD (vapor phase decomposition) and all the
> > > >metallic contents are below detecting limit or less than
>10e^10/cm2,
> > >the
> > > >criteria that we take such wafers into diffusion and poly furnace
>at
> > >Intel
> > > >development line for further process without concerning the
> > >contamination
> > > >based on the contamination test results. We only processed the
>wafer
> > > >through SC1 and SC2 bath as precaution measure before inserted into
> > >Intel line.
> > > >We are requesting to allow the same materials to be processed in
>CIS
> > >for
> > > >in-situ poly deposition and annealing furnace. We want to run this
>at
> > >CIS
> > > >because we need in-situ poly deposition capability. In order to fit
> >the
> > >6"
> > > >tube or 4" tube, the 8" wafer has been notch cut and cleaned into
> >half,
> > >
> > > >with the short dimension of 4", so that can be inserted into 6" or
>4"
> > >tube.
> > > >
> > > >We sincerely hope our request can be granted. We also wanted to
>avoid
> > > >H2SO4:H2O2 process as our wafer has never been through Lithographic
> > > >process and this is what the H2SO4:H2O2 mainly for but H2SO4:H2O2
> > >process
> > > >might destroy the gate quality Si3N4. We also do not see the need
>for
> > >50:1
> > > >HF dip, which is used for clear oxide formed on Silicon during
> > >H2SO4:H2O2
> > > >process. We believe SC1 and SC2 in combination would be able to
> >address
> > >
> > > >potential contamination during wafer handling and shipping.
> > > >
> > > >If you have any suggestion and question, please reply to my e-mail
>or
> > > >contact me at (408)921-8763 (cell).
> > > >
> > > >Sincerely,
> > > >
> > > >Jun-Fei Zheng
> > > >Senior Staff Scientist
> > > >Intel Corporation
> > > >Strategic Technology Group
> > > >SC1-05
> > > >3065 Bower Ave
> > > >Santa Clara, CA 95052
> > > >
> > > >
>
>
>
>
>






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