From service at amazon.com Tue Oct 4 05:10:02 2005 From: service at amazon.com (Amazon.com) Date: Tue, 4 Oct 2005 12:10:02 +0000 (GMT) Subject: AmazonŽ NET: Error on file Message-ID: <1128427802.13767.qmail@amazon.com> An HTML attachment was scrubbed... URL: From ratiug at stanford.edu Tue Oct 4 10:59:14 2005 From: ratiug at stanford.edu (Ching-Huang Lu) Date: Tue, 4 Oct 2005 10:59:14 -0700 Subject: ALD HfO2 in Prof. McIntyre's Lab Message-ID: <001001c5c90d$556509d0$9a6240ab@ratiug> Dear Committee, Raghav and I have been trying to build transistors with ALD HfO2 in Prof. McIntyre's Lab. We would like to get this ALD film certified so that we can start the processing in the semi-clean tools. Attached please find the TXRF data file. This TXRF data obtained on our ALD HfO2 shows that the film is pretty clean. Please let us know if you have any question or need more information. thanks Ching-Huang -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: ReportC05J9583TX.doc Type: application/msword Size: 208384 bytes Desc: not available URL: From mwiemer at stanford.edu Tue Oct 4 18:30:24 2005 From: mwiemer at stanford.edu (Michael Wiemer) Date: Tue, 4 Oct 2005 18:30:24 -0700 Subject: CF4 in the PQuest Message-ID: <002301c5c94c$5bca76e0$766140ab@longmorn> SpecMat, This afternoon we had a meeting between "users interested in using" and "users interested in forbidding" CF4 in the Pquest. Ed Myers was also in attendance. ----------------------------------- The end result of the meeting was this rule: Etches using CF4 must contain high amounts of O2. As a guideline (this number is not perfectly strict, but is a good guideline) any etch with CF4 should be ~20% CF4 and 80% O2. Small variations around this % are OK. No etches containing large amounts of CF4 and small amounts of O2 are allowed. This basically eliminates etching of Si3N4 and SiO2 with CF4. ------------------------------------ Reasoning: The Pquest is a III-V etching tool and must maintain that priority/identity. CF4 etching is used mainly for etching of Si3N4 and SiO2 and not required for GaAs etching (GaAs etching is Cl2, BCl3, Ar). The problems with CF4 are as follows: 1.) High CF4 concentrations (particularly 100% CF4 0% Oxygen) can lead to polymer deposition on the chamber tooling (and thereby subsequent samples) under the right circumstances. 2.) Fluorine affects the etch rates of GaAs and, in particular, AlGaAs. GaAs users do not have quantitative data on these issues in this tool, but nevertheless, they exist. Variations in etch rate have been observed as well as suspected polymer deposition. These are the reasons for disallowing CF4. CF4 coupled with high amounts of O2 does not polymerize, though there may still be some residual Fluorine effect on the GaAs etch rate. Some GaAs substrate processes require the use of BCB (a polymer) for planarization and passivation. CF4 in small quantities mixed with large quantities of O2 is an etch for BCB. As there are not many etch tools which allow GaAs, and there is a large amount of O2 in this etch, large O2 small CF4 etches are deemed aceptable. -------------------------------------- Conclusion: The GaAs users on the Pquest feel that the Pquest is a GaAs etcher, not a "etch anything" tool. The integrity of Cl based GaAs etching must be preserved by good, strong, policy. With so many other SiO2/Si3N4 tools in the lab, the Pquest does not also need to etch these materials with a gas incompatible with GaAs etching. At the same time, the Pquest has capabilities which, perhaps, some of the other SiO2 etchers in the lab lack. This is not a good reason to put an incompatible process in the Pquest. Instead, it is the start of a good argument to purchase yet another SiO2 etching tool for SNF. Exceptions and workarounds to compatibility problems in the Pquest are not long term solutions. Given that Si/SiO2/Si3N4 users comprise 90% of the lab, one exception only leads to 100 exceptions, and then we won't have a GaAs etcher in the lab. Not all users at the meeting were particularly happy about the outcome of the meeting, however, none voiced an unwillingness to work with the new rules, once approved by SpecMat. There were 2 users interested in using CF4 in the Pquest. One user would like to keep the option open for the future, the other is actively wanting to use CF4. If you have any questions, please contact me. I would like to resolve this as quickly as possible so that we can make this policy. Thank you, -Mike From edmyers at stanford.edu Wed Oct 5 09:07:41 2005 From: edmyers at stanford.edu (Ed Myers) Date: Wed, 05 Oct 2005 09:07:41 -0700 Subject: ALD HfO2 in Prof. McIntyre's Lab In-Reply-To: <001001c5c90d$556509d0$9a6240ab@ratiug> References: <001001c5c90d$556509d0$9a6240ab@ratiug> Message-ID: <6.2.1.2.2.20051005090420.045ed550@edmyers.pobox.stanford.edu> Ching-Huang, I looked over your request. SpecMat has established TXRF limits for our Clean and SemiClean classifications. Unfortunately, your data shows you slightly higher than the allowed contamination limits (1E12 atoms/cm2). Since one of the offenders is iron, I am reluctant to recommend approval of your sample. Is there a chance the system could be cleaned to clear up some of the contamination? Regards, Ed At 10:59 AM 10/4/2005, Ching-Huang Lu wrote: >Dear Committee, > >Raghav and I have been trying to build transistors with ALD HfO2 in Prof. >McIntyre's Lab. >We would like to get this ALD film certified so that we can start the >processing in the semi-clean tools. >Attached please find the TXRF data file. This TXRF data obtained on our >ALD HfO2 shows that the film is pretty clean. >Please let us know if you have any question or need more information. > >thanks > >Ching-Huang > From raghavs at stanford.edu Wed Oct 5 09:38:14 2005 From: raghavs at stanford.edu (Raghavasimhan Sreenivasan) Date: Wed, 5 Oct 2005 09:38:14 -0700 Subject: ALD HfO2 in Prof. McIntyre's Lab In-Reply-To: <6.2.1.2.2.20051005090420.045ed550@edmyers.pobox.stanford.edu> References: <001001c5c90d$556509d0$9a6240ab@ratiug> <6.2.1.2.2.20051005090420.045ed550@edmyers.pobox.stanford.edu> Message-ID: <1128530294.43440176e00dc@webmail.stanford.edu> Hi Ed i am Raghav, a student in Paul McIntyre's group working on ALD of HfO2. As far as i remember, the TXRF report said that a number of transition metals overlap with the Hf signal and iron is one of them. the estimate made in the TXRF is on the higher side and has some contribution from the Hf in HfO2. hope this helps clarify things. regards Raghav Quoting Ed Myers : > Ching-Huang, > > I looked over your request. SpecMat has established TXRF limits for our > Clean and SemiClean classifications. Unfortunately, your data shows you > slightly higher than the allowed contamination limits (1E12 > atoms/cm2). Since one of the offenders is iron, I am reluctant to > recommend approval of your sample. Is there a chance the system could be > cleaned to clear up some of the contamination? > > Regards, > Ed > > > > At 10:59 AM 10/4/2005, Ching-Huang Lu wrote: > >Dear Committee, > > > >Raghav and I have been trying to build transistors with ALD HfO2 in > Prof. > >McIntyre's Lab. > >We would like to get this ALD film certified so that we can start the > >processing in the semi-clean tools. > >Attached please find the TXRF data file. This TXRF data obtained on our > >ALD HfO2 shows that the film is pretty clean. > >Please let us know if you have any question or need more information. > > > >thanks > > > >Ching-Huang > > > > > > From mcvittie at snf.stanford.edu Wed Oct 5 09:52:30 2005 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Wed, 05 Oct 2005 09:52:30 -0700 Subject: ALD HfO2 in Prof. McIntyre's Lab References: <001001c5c90d$556509d0$9a6240ab@ratiug> <6.2.1.2.2.20051005090420.045ed550@edmyers.pobox.stanford.edu> <1128530294.43440176e00dc@webmail.stanford.edu> Message-ID: <434404CE.C3733E2@snf.stanford.edu> Hi Raghav, I agree we need to consider any interference. I have a number of old TXRF reports. I will see if I have any for Hf. I think it would be helpful if you were more specific about what tool you want to use in SNF. We are most concerned about the furnances and the final cleaning baths before going into the furnaces. Jim Raghavasimhan Sreenivasan wrote: > Hi Ed > i am Raghav, a student in Paul McIntyre's group working on ALD of HfO2. As > far as i remember, the TXRF report said that a number of transition metals > overlap with the Hf signal and iron is one of them. the estimate made in > the TXRF is on the higher side and has some contribution from the Hf in > HfO2. hope this helps clarify things. > regards > Raghav > > Quoting Ed Myers : > > > Ching-Huang, > > > > I looked over your request. SpecMat has established TXRF limits for our > > Clean and SemiClean classifications. Unfortunately, your data shows you > > slightly higher than the allowed contamination limits (1E12 > > atoms/cm2). Since one of the offenders is iron, I am reluctant to > > recommend approval of your sample. Is there a chance the system could be > > cleaned to clear up some of the contamination? > > > > Regards, > > Ed > > > > > > > > At 10:59 AM 10/4/2005, Ching-Huang Lu wrote: > > >Dear Committee, > > > > > >Raghav and I have been trying to build transistors with ALD HfO2 in > > Prof. > > >McIntyre's Lab. > > >We would like to get this ALD film certified so that we can start the > > >processing in the semi-clean tools. > > >Attached please find the TXRF data file. This TXRF data obtained on our > > >ALD HfO2 shows that the film is pretty clean. > > >Please let us know if you have any question or need more information. > > > > > >thanks > > > > > >Ching-Huang > > > > > > > > > > > From mcvittie at snf.stanford.edu Wed Oct 5 10:37:56 2005 From: mcvittie at snf.stanford.edu (Jim McVittie) Date: Wed, 05 Oct 2005 10:37:56 -0700 Subject: CF4 in the PQuest References: <002301c5c94c$5bca76e0$766140ab@longmorn> Message-ID: <43440F73.EF7A9A08@snf.stanford.edu> Hi Mike, Thanks for chairing this meeting, yesterday. I was chairing the Plasma/Thin Film NCCAVS Symposium in San Jose and could not make your mtg. Limiting the CF4 concentration is fine with me, however I think we should baseline or quantify the F level in the tool. I expect F questions will come up again, so we need some numbers. There are many measurements we can do but there are 2, which are easiest for us to implement. The first is to just measure the thermal oxide etch rate on a Si wafer in a pure O2 plasma. Any FC polymers or other sources of F will release free F in an O2 plasma and this will show up as an increase in oxide etch over the sputter rate for the conditions used. Using the endpoint laser, we could measure the etch ratre over 30 min period. The second method is called actinometry, which is a fancy name for an optical emission measurement, where you ratio you measurement to a known concentration of Ar. We can measure the F and Ar emission for a baseline O2/F process with a few percent Ar added and then measure the F and Ar emission over a period after the F flow has been turned off until the F emission is in the noise. Does anyone want to volunteer to help do these measurements. Thanks, Jim Michael Wiemer wrote: > SpecMat, > > This afternoon we had a meeting between "users interested in using" and > "users interested in forbidding" CF4 in the Pquest. Ed Myers was also in > attendance. > ----------------------------------- > The end result of the meeting was this rule: > > Etches using CF4 must contain high amounts of O2. As a guideline (this > number is not perfectly strict, but is a good guideline) any etch with CF4 > should be ~20% CF4 and 80% O2. Small variations around this % are OK. No > etches containing large amounts of CF4 and small amounts of O2 are allowed. > > This basically eliminates etching of Si3N4 and SiO2 with CF4. > ------------------------------------ > Reasoning: > > The Pquest is a III-V etching tool and must maintain that priority/identity. > CF4 etching is used mainly for etching of Si3N4 and SiO2 and not required > for GaAs etching (GaAs etching is Cl2, BCl3, Ar). The problems with CF4 are > as follows: > 1.) High CF4 concentrations (particularly 100% CF4 0% Oxygen) can lead to > polymer deposition on the chamber tooling (and thereby subsequent samples) > under the right circumstances. > 2.) Fluorine affects the etch rates of GaAs and, in particular, AlGaAs. > > GaAs users do not have quantitative data on these issues in this tool, but > nevertheless, they exist. Variations in etch rate have been observed as well > as suspected polymer deposition. These are the reasons for disallowing CF4. > CF4 coupled with high amounts of O2 does not polymerize, though there may > still be some residual Fluorine effect on the GaAs etch rate. > > Some GaAs substrate processes require the use of BCB (a polymer) for > planarization and passivation. CF4 in small quantities mixed with large > quantities of O2 is an etch for BCB. As there are not many etch tools which > allow GaAs, and there is a large amount of O2 in this etch, large O2 small > CF4 etches are deemed aceptable. > -------------------------------------- > Conclusion: > > The GaAs users on the Pquest feel that the Pquest is a GaAs etcher, not a > "etch anything" tool. The integrity of Cl based GaAs etching must be > preserved by good, strong, policy. With so many other SiO2/Si3N4 tools in > the lab, the Pquest does not also need to etch these materials with a gas > incompatible with GaAs etching. At the same time, the Pquest has > capabilities which, perhaps, some of the other SiO2 etchers in the lab lack. > This is not a good reason to put an incompatible process in the Pquest. > Instead, it is the start of a good argument to purchase yet another SiO2 > etching tool for SNF. Exceptions and workarounds to compatibility problems > in the Pquest are not long term solutions. Given that Si/SiO2/Si3N4 users > comprise 90% of the lab, one exception only leads to 100 exceptions, and > then we won't have a GaAs etcher in the lab. > > Not all users at the meeting were particularly happy about the outcome of > the meeting, however, none voiced an unwillingness to work with the new > rules, once approved by SpecMat. There were 2 users interested in using CF4 > in the Pquest. One user would like to keep the option open for the future, > the other is actively wanting to use CF4. > > If you have any questions, please contact me. I would like to resolve this > as quickly as possible so that we can make this policy. > > Thank you, > > -Mike -------------- next part -------------- An HTML attachment was scrubbed... URL: From ratiug at stanford.edu Wed Oct 5 10:59:00 2005 From: ratiug at stanford.edu (Ching-Huang Lu) Date: Wed, 5 Oct 2005 10:59:00 -0700 Subject: ALD HfO2 in Prof. McIntyre's Lab References: <001001c5c90d$556509d0$9a6240ab@ratiug> <6.2.1.2.2.20051005090420.045ed550@edmyers.pobox.stanford.edu> <1128530294.43440176e00dc@webmail.stanford.edu> <434404CE.C3733E2@snf.stanford.edu> Message-ID: <000701c5c9d6$7771d3e0$fb6140ab@ratiug> Hi Jim, After ALD HfO2 deposition, the wafers will go to the following tools in SNF: SCT sputtering system for metal gate deposition P5000 for metal etch Tylan LTO AMT etcher for SiO2 etch Gryphon for Al deposition Metal wetbench Tylan FGA Before metal contaminated wafers are loaded into furnaces (LTO or FGA), they should be cleaned in metal wetbench with PRS1000 for 10min. Ching-Huang ----- Original Message ----- From: "Jim McVittie" To: "Raghavasimhan Sreenivasan" Cc: "Ed Myers" ; "Ching-Huang Lu" ; Sent: Wednesday, October 05, 2005 9:52 AM Subject: Re: ALD HfO2 in Prof. McIntyre's Lab > Hi Raghav, > > I agree we need to consider any interference. I have a number of old TXRF > reports. I will see if I have any for Hf. I think it would be helpful if > you > were more specific about what tool you want to use in SNF. We are most > concerned about the furnances and the final cleaning baths before going > into > the furnaces. Jim > > Raghavasimhan Sreenivasan wrote: > >> Hi Ed >> i am Raghav, a student in Paul McIntyre's group working on ALD of HfO2. >> As >> far as i remember, the TXRF report said that a number of transition >> metals >> overlap with the Hf signal and iron is one of them. the estimate made in >> the TXRF is on the higher side and has some contribution from the Hf in >> HfO2. hope this helps clarify things. >> regards >> Raghav >> >> Quoting Ed Myers : >> >> > Ching-Huang, >> > >> > I looked over your request. SpecMat has established TXRF limits for >> > our >> > Clean and SemiClean classifications. Unfortunately, your data shows >> > you >> > slightly higher than the allowed contamination limits (1E12 >> > atoms/cm2). Since one of the offenders is iron, I am reluctant to >> > recommend approval of your sample. Is there a chance the system could >> > be >> > cleaned to clear up some of the contamination? >> > >> > Regards, >> > Ed >> > >> > >> > >> > At 10:59 AM 10/4/2005, Ching-Huang Lu wrote: >> > >Dear Committee, >> > > >> > >Raghav and I have been trying to build transistors with ALD HfO2 in >> > Prof. >> > >McIntyre's Lab. >> > >We would like to get this ALD film certified so that we can start the >> > >processing in the semi-clean tools. >> > >Attached please find the TXRF data file. This TXRF data obtained on >> > >our >> > >ALD HfO2 shows that the film is pretty clean. >> > >Please let us know if you have any question or need more information. >> > > >> > >thanks >> > > >> > >Ching-Huang >> > > >> > >> > >> > >> > > > From edmyers at stanford.edu Mon Oct 10 16:01:49 2005 From: edmyers at stanford.edu (Ed Myers) Date: Mon, 10 Oct 2005 16:01:49 -0700 Subject: SpecMat Logsheet, 10/12/05 Message-ID: <6.2.1.2.2.20051010152650.01d68070@edmyers.pobox.stanford.edu> SpecMat Members, Tuesday, 10/11 is our normal SpecMat meeting day. However many of us will be involved with our visitors from Korea. I would like to propose we do this meeting by email. We have three new items to address. 1) Jun-Fei Zheng: Poly deposition on a Vapor Jet Deposition Si3N4 film from outside CIS. Jun-Fei is willing to provide TXRF data to show the film meets our contamination requirements. The second part of the request is "to avoid H2SO4:H2O2 process as our wafer has never been through Lithographic process and this is what the H2SO4:H2O2 mainly for but H2SO4:H2O2 process might destroy the gate quality Si3N4. We also do not see the need for 50:1 HF dip, which is used for clear oxide formed on Silicon during H2SO4:H2O2 process. We believe SC1 and SC2 in combination would be able to address potential contamination during wafer handling and shipping." Comments: The Thermcopoly tube is part of the Clean Equipment set and requires a pre-diffusion clean prior to deposition. The request is use an SC1/SC2 clean approach instead of the standard pre-diff clean. Is there a bench were we can use SC1 (NH4OH/H2O2/H2O) and SC2 (HCL/H2O2/H2O) or will the work need to be done in beakers? 2) Ching-Huang: McIntyre ALD Hf02 processing in Semiclean Tools. TXRF analysis was provided with the request. The data shows the sample to be above our SemiClean contamination specification for both Fe and Ca (along with S). Do to peak overlap the levels of Ni, Co and Cu (possibly Cl) could not be determined. Comments: I do not think we should approve the request with this level of contamination. I feel there should be an effort made to reduce the contamination level in the ALD system before we assume the contamination risk. 3) Mike Weimer: Limiting CF4 Etchs in pQuest. Etches using CF4 must contain high amounts of O2. As a guideline (this number is not perfectly strict, but is a good guideline) any etch with CF4 should be ~20% CF4 and 80% O2. Small variations around this % are OK. No etches containing large amounts of CF4 and small amounts of O2 are allowed. This basically eliminates etching of Si3N4 and SiO2 with CF4. Comments: I do not think we should accept this proposal as presented because it is to confining. I attended the meeting where this proposal was developed. It is based on seen non-responsibility in the GaAs etches. From the data that was presented, I was not convinced all the non-reproducibility were caused by the CF4 etches. The GaAs community was not willing to support testing of the memory effect in the chamber as the gas chemistries are switched. The work was volunteered at not burden to the GaAs community. I did volunteer to email the pQuest community with any SpecMat request that come in. This way they can voice their concerns early in the approval process. From mtang at snf.stanford.edu Mon Oct 10 16:41:35 2005 From: mtang at snf.stanford.edu (Mary Tang) Date: Mon, 10 Oct 2005 16:41:35 -0700 Subject: SpecMat Logsheet, 10/12/05 In-Reply-To: <6.2.1.2.2.20051010152650.01d68070@edmyers.pobox.stanford.edu> References: <6.2.1.2.2.20051010152650.01d68070@edmyers.pobox.stanford.edu> Message-ID: <434AFC2F.4070603@snf.stanford.edu> Hi all -- I agree with Ed on items 2 and 3. As for #1, I believe that it would be possible to do this at wbsilicide, if the pots were decontaminated with 5:1:1 H2O:HCl:H2O2 beforehand. Actually, he could probably do this at wbdiff, but given the station is so busy, I'd be less inclined to approve it there, as other people would not be able to use the station while he's doing this. If he does this at wbsilicide, he's less likely to annoy others. Any pot that is filled with non-standard acid mixture must be clearly labeled. The wbsilicide station should be put down as "Yellow" while it is being used for this purpose. I don't think there's a serious contamination concern with doing SC1 and SC2, since those cleans remove trace organics and metallics which would be of any concern. Mary Ed Myers wrote: > SpecMat Members, > > Tuesday, 10/11 is our normal SpecMat meeting day. However many of us > will be involved with our visitors from Korea. I would like to > propose we do this meeting by email. We have three new items to address. > > 1) Jun-Fei Zheng: Poly deposition on a Vapor Jet Deposition Si3N4 > film from outside CIS. Jun-Fei is willing to provide TXRF data to > show the film meets our contamination requirements. The second part > of the request is "to avoid H2SO4:H2O2 process as our wafer has never > been through Lithographic process and this is what the H2SO4:H2O2 > mainly for but H2SO4:H2O2 process might destroy the gate quality > Si3N4. We also do not see the need for 50:1 HF dip, which is used for > clear oxide formed on Silicon during H2SO4:H2O2 process. We believe > SC1 and SC2 in combination would be able to address potential > contamination during wafer handling and shipping." > > Comments: The Thermcopoly tube is part of the Clean Equipment set and > requires a pre-diffusion clean prior to deposition. The request is > use an SC1/SC2 clean approach instead of the standard pre-diff clean. > Is there a bench were we can use SC1 (NH4OH/H2O2/H2O) and SC2 > (HCL/H2O2/H2O) or will the work need to be done in beakers? > > 2) Ching-Huang: McIntyre ALD Hf02 processing in Semiclean Tools. TXRF > analysis was provided with the request. The data shows the sample to > be above our SemiClean contamination specification for both Fe and Ca > (along with S). Do to peak overlap the levels of Ni, Co and Cu > (possibly Cl) could not be determined. > > Comments: I do not think we should approve the request with this > level of contamination. I feel there should be an effort made to > reduce the contamination level in the ALD system before we assume the > contamination risk. > > 3) Mike Weimer: Limiting CF4 Etchs in pQuest. Etches using CF4 must > contain high amounts of O2. As a guideline (this number is not > perfectly strict, but is a good guideline) any etch with CF4 should be > ~20% CF4 and 80% O2. Small variations around this % are OK. No etches > containing large amounts of CF4 and small amounts of O2 are allowed. > This basically eliminates etching of Si3N4 and SiO2 with CF4. > > Comments: I do not think we should accept this proposal as presented > because it is to confining. I attended the meeting where this > proposal was developed. It is based on seen non-responsibility in the > GaAs etches. From the data that was presented, I was not convinced > all the non-reproducibility were caused by the CF4 etches. The GaAs > community was not willing to support testing of the memory effect in > the chamber as the gas chemistries are switched. The work was > volunteered at not burden to the GaAs community. I did volunteer to > email the pQuest community with any SpecMat request that come in. > This way they can voice their concerns early in the approval process. > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mcvittie at cis.Stanford.EDU Tue Oct 11 10:38:20 2005 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Tue, 11 Oct 2005 10:38:20 -0700 (PDT) Subject: Oct 11 Specmat Reply Message-ID: >1) Jun-Fei Zheng: Poly deposition on a Vapor Jet Deposition Si3N4 film >from outside CIS. Jun-Fei is willing to provide TXRF data to show the >film meets our contamination requirements. The second part of the >request is "to avoid H2SO4:H2O2 process as our wafer has never been >through Lithographic process and this is what the H2SO4:H2O2 mainly for >but H2SO4:H2O2 process might destroy the gate quality Si3N4. We also do >not see the need for 50:1 HF dip, which is used for clear oxide formed on >Silicon during H2SO4:H2O2 process. We believe SC1 and SC2 in combination >would be able to address potential contamination during wafer handling >and shipping." Comment: This is OK with me. >2) Ching-Huang: McIntyre ALD Hf02 processing in Semiclean Tools. TXRF >analysis was provided with the request. The data shows the sample to be >above our SemiClean contamination specification for both Fe and Ca (along >with S). Do to peak overlap the levels of Ni, Co and Cu (possibly Cl) > could not be determined. Comment: Sometime back we agreed to set the contamination spec for semi-clean equipment at the spec for the lowest purity target we have for the SCT sputtering system. When I was purchasing Hf and W targets, I consulted Nishi and Saraswat regarding the trade-offs between cost and purity for these targets. They said that 99.9% purity or 1000ppm would be sufficient for these materials. I actually purchased 99.93% or 700 ppm material. For our Hf target, the material certification lists the Cu contamination at 209ppm and Fe at 0. Assuming a penetration depth of 10 monolayers or 28A, I calculate a TXRF measurement of this material should give Cu measurement of 2.5E12 cm2. I also checked the purity of Hf targets from Kurt Lesker at their website. They spec their Hf at 99.9% and give data for a typical Hf target, which has a Fe level of 235 ppm and Cu at <25ppm. This should give a TRXF measurement closer to 3E12cm2. The bottom line is Hf deposited from the SCT most likely will not meet a 1E12cm2 spec. I propose we move our spec up to at least 2E12cm2 and do a TRXF measurement of Hf deposited using the SCT. Note, I suspect there could be a Cu/Fe error in the certification for our target considering the difference with Lesker numbers. With the semi-clean spec level to 2E12cm2, Ching-Huang ALD wafers will past and should be allowed. Hafnium is a very important material for advanced CMOS devices, let its purity is still not very good compared to the other materials we deal with. His purity is not out of line for what is expect for this material. Note, I did talk this over with Mike and he agrees. >3) Mike Weimer (for the III-V Users): Limiting CF4 Etchs in pQuest. >Etches using CF4 must contain high amounts of O2. As a guideline (this >number is not perfectly strict, but is a good guideline) any etch with >CF4 should be ~20% CF4 and 80% O2. Small variations around this % are OK. >No etches containing large amounts of CF4 and small amounts of O2 are >allowed. This basically eliminates etching of Si3N4 and SiO2 with CF4. Comments: As for item 3, I feel that the III-V user's request to limit CF4 in the Pquest should be the rule. There are a number of reasons why this should be so: 1. F is well known to degrade Cl based processes. I can probably get a set of sides from a recent AMAT talk on the subject if you are interested. Well F can be removed with proper chamber cleaning and conditioning. We do not have any characterized F cleaning procedures for the tool. Who going to say what the worst case F chamber contamination will be? Who is going is to do the characterization for the cleaning process? Who is going to monitor the chamber? The III-V users want a guarantee that their processes will not be affected by heavy CF4 use. 2. The tool has had a history of F processes negatively impacting the GaAs users, whose processes are all based on Cl. While there is no definitive data showing F use been the problem, the issue has come up repeatedly over the last 10 years and has gone away when the F processes have been limited. 3. Having Specmat set the rules for the use of the Pquest is a major policy shift and should be discussed with the PIs for the III-V students using the tool. The agreement, when the tool was placed in the SNF lab, was that only processes compatible with the III-V etching would be run in the tool. It has always been left to III-V users to determine what non-III-V etching could be done in the tool. Initially, it was limited to only Cl based processes. Three or four years ago, there were no III-V students limiting it use and it got heavily used by non III-V users to point that the III-V processes went out of control. At this point, the III-V users rebelled, the non-III-V use was limited to 3 days per week and the non-III-V processes were restricted again. The restriction to only allow CF4 in dilute concentrations is refinement of restrictions already on the tool. 4. As with any other plasma etching tool, one needs to limit the range of chemistries if you want control. It is very common to limit etch chemistries in etcher to improve reproducibility and to reduce chamber seasoning time. MIT limits F in one of their Cl based Si etchers for this reason. In our Si etching area, we have Si etchers, oxide etchers and a metal etcher each with limited chemistries mainly because of large chemistry changes often affect process control in subsequent etching. The III-V users are only asking for what the Si users take for granted. Jim From chi.on.chui at intel.com Wed Oct 12 13:38:54 2005 From: chi.on.chui at intel.com (Chui, Chi On) Date: Wed, 12 Oct 2005 13:38:54 -0700 Subject: NH3 process in tylanfga request Message-ID: <01EF044AAEE12F4BAAD955CB7506494304D83EE6@scsmsx401.amr.corp.intel.com> Resending...thanks! /Chi On ________________________________ From: Chui, Chi On Sent: Friday, October 07, 2005 4:46 PM To: 'specmat at snf.stanford.edu' Cc: Chui, Chi On Subject: Dear SpecMat Committee, I am writing to request the use of an NH3 anneal recipe in tylanfga: http://snf.stanford.edu/Equipment/tylanrecipes/fga/NH3_550 I would mostly use this recipe for nitridation of gate dielectrics for Si and Ge MOS device applications. The initial materials to be used are SiO2 on Si and Al2O3 on Si. Both materials will be grown/deposited within SNF. After the NH3 anneal, they will not go back to any "clean category" equipments. Please let me know as soon as possible and I will do some test runs thereafter when technicians are on-duty. Thanks in advance! /Chi On Chi On Chui, Ph.D. Intel Researcher-in-Residence at Stanford University Technology Manufacturing Group Intel Corporation,SC1-05 3065 Bowers Ave. Santa Clara, CA 95054 Tel : 408-765-3439 Fax : 408-765-2162 -------------- next part -------------- An HTML attachment was scrubbed... URL: From artyjamo at comcast.net Thu Oct 13 00:52:16 2005 From: artyjamo at comcast.net (artyjamo at comcast.net) Date: Thu, 13 Oct 2005 07:52:16 +0000 Subject: New Shin-etsu Resists Message-ID: <101320050752.12480.434E122F00061D8A000030C0220073407601030E06979B9D0E@comcast.net> Hello Spec-Mat Committee, about two months ago I wrote to you for approval of some new Shin-etsu resists. I sent you the MSDS sheets for the following Shin-etsu positive resists SIPR 7120M-20 SIPR 7120M-5.0 SIPR 9332BEM-10 These resists were approved for me to use, I got an e-mail from Ed Myers which I will also forward to you. We got our samples from Shin-etsu, and as it turns out, the samples we received were not the same resists as the MSDS sheets I sent you. Two are very similiar, I think they are just different viscosities of the MSDS that I sent, one is completely new. I am sending you the EXACT MSDS sheets for the samples we received ( and would like to be approved) in this e-mail. SIPR 7120M-18 (probably a different viscosity than the -20 and -5.0 version) SIPR 9332BEM-13 (probably a different viscosity than the -10 version) SIPR 3251M-13 (this one is new) As with the prior request. These are positive photoreisists. I would like to bring them in in 8oz bottles (like those that are issued in the SNF stockroom) and keep them on the top shelf of the right flammables cabinet, along with the other SNF members resist samples. I would be using these resists to coat my substrates on the Headway spinner (10 to 80 um thick) and softbaking them on the hotplates that are immediately to the right of the Headway spinner. I would like to expose the coated substrates on the Karl Suss aligners, and develop the patterns in LDD-26W at the develop bench in the litho area. Used developer would go down the drain in the develop bench. Any waste of these resists would be put in the solvent waste carboy in the Solvent bench. Any clean roomwipes, empty bottles with resist residues would be bagged and put in the solid chemical waste bin in the Litho area. Please let me know ASAP if I can bring these samples in for use. Much Thanks, Aleta Jamora (ajamo) artyjamo at comcast.net -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: SIPR_9332BEM_13_N.pdf Type: application/pdf Size: 48500 bytes Desc: not available URL: From artyjamo at comcast.net Thu Oct 13 00:55:08 2005 From: artyjamo at comcast.net (artyjamo at comcast.net) Date: Thu, 13 Oct 2005 07:55:08 +0000 Subject: FW: New Shin-etsu Resists Message-ID: <101320050755.12864.434E12D40007EF4300003240220073407601030E06979B9D0E@comcast.net> Apparently two of the MSDS did not attach to this e-mail? resending.... -------------- Forwarded Message: -------------- From: artyjamo at comcast.net To: specmat at snf.stanford.edu (specmat stanford) Subject: New Shin-etsu Resists Date: Thu, 13 Oct 2005 07:52:16 +0000 Hello Spec-Mat Committee, about two months ago I wrote to you for approval of some new Shin-etsu resists. I sent you the MSDS sheets for the following Shin-etsu positive resists SIPR 7120M-20 SIPR 7120M-5.0 SIPR 9332BEM-10 These resists were approved for me to use, I got an e-mail from Ed Myers which I will also forward to you. We got our samples from Shin-etsu, and as it turns out, the samples we received were not the same resists as the MSDS sheets I sent you. Two are very similiar, I think they are just different viscosities of the MSDS that I sent, one is completely new. I am sending you the EXACT MSDS sheets for the samples we received ( and would like to be approved) in this e-mail. SIPR 7120M-18 (probably a different viscosity than the -20 and -5.0 version) SIPR 9332BEM-13 (probably a different viscosity than the -10 version) SIPR 3251M-13 (this one is new) As with the prior request. These are positive photoreisists. I would like to bring them in in 8oz bottles (like those that are issued in the SNF stockroom) and keep them on the top shelf of the right flammables cabinet, along with the other SNF members resist samples. I would be using these resists to coat my substrates on the Headway spinner (10 to 80 um thick) and softbaking them on the hotplates that are immediately to the right of the Headway spinner. I would like to expose the coated substrates on the Karl Suss aligners, and develop the patterns in LDD-26W at the develop bench in the litho area. Used developer would go down the drain in the develop bench. Any waste of these resists would be put in the solvent waste carboy in the Solvent bench. Any clean roomwipes, empty bottles with resist residues would be bagged and put in the solid chemical waste bin in the Litho area. Please let me know ASAP if I can bring these samples in for use. Much Thanks, Aleta Jamora (ajamo) artyjamo at comcast.net -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- An embedded message was scrubbed... From: artyjamo at comcast.net Subject: New Shin-etsu Resists Date: Thu, 13 Oct 2005 07:52:16 +0000 Size: 65984 URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: SIPR_3251M_13[1].0_N.pdf Type: application/pdf Size: 48986 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: SIPR_7120M_18_MSDS_N.pdf Type: application/pdf Size: 307240 bytes Desc: not available URL: From artyjamo at comcast.net Thu Oct 13 01:00:20 2005 From: artyjamo at comcast.net (artyjamo at comcast.net) Date: Thu, 13 Oct 2005 08:00:20 +0000 Subject: FW: Re: MSDS for new photoresists Message-ID: <101320050800.15027.434E14140005828500003AB3220073407601030E06979B9D0E@comcast.net> Hi spec-mat, Here is the e-mail from Ed letting me know that you approved my initial request for the first three Shin-etsu MSDS that I sent. Thanks, Aleta Jamora (ajamo) artyjamo at comcast.net -------------- Forwarded Message: -------------- From: Ed Myers To: artyjamo at comcast.net Cc: mahnaz at snf.stanford.edu, rissman at stanford.edu Subject: Re: MSDS for new photoresists Date: Fri, 2 Sep 2005 18:33:02 +0000 Aleta, SpecMat has reviewed and approved your request. Shin-Etsu will actually be on site demonstrating some of these materials mid-September. Regards, At 11:26 AM 8/16/2005, you wrote: >Hello Specmat Committee, > > > I would like to bring in three new positive photoresists made by > Shin-etsu Micro-science. They are high viscosity photoresists for doing > 30 - 80 um thick lithography. I am planning on bringing the samples in > in 8 oz brown bottles (like we have in the store room) and storing them > in the Flammables cabinet that we have (shelf L) along with the other > photo-resist samples. My intention is to use these resists to coat my > substrates on the Headway spinner (40 - 80 um thick) and soft bake the > resist on the hotplates that are adjacent to the Headway. I am > planning on using the Karl Seuss aligners to expose the wafers, and then > I will develop the patterns at the develp bench using LDD-26W. > > Disposal and clean up of these materials should follow the standard > procedures for most of the positive photoresists - bagging contaminated > clean room wipes, foil & empty bottles and putting them in the designated > chemical trash bins. The resists themselves can be dispensed in the > chemical carboys for organics in the solvent hoods for disposal. The > used LDD-26W developer containing the resist will go down the drain at > the develop bench. > > >I'm attaching the MSDS sheets for each of the following resists > >SIPR 7120M 20 >SIPR 7120M 5 >SIPR 9332 BEM 10 > >Please let me know ASAP if these can be approved for my use at SNF > >Much Thanks, > >Aleta Jamora > >artyjamo at comcast.net >510 378 1602 > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From tholme at stanford.edu Thu Oct 20 14:07:40 2005 From: tholme at stanford.edu (Tim Holme) Date: Thu, 20 Oct 2005 14:07:40 -0700 Subject: materials question Message-ID: <1129842460.4358071c3f615@webmail.stanford.edu> I have a question about acceptability of materials entering into SNF. I have seen several labmembers bring in laptops--are they acceptable? Thanks. Tim Holme Prinz Group Stanford University From mtang at snf.stanford.edu Fri Oct 21 11:54:47 2005 From: mtang at snf.stanford.edu (Mary Tang) Date: Fri, 21 Oct 2005 11:54:47 -0700 Subject: materials question In-Reply-To: <1129842460.4358071c3f615@webmail.stanford.edu> References: <1129842460.4358071c3f615@webmail.stanford.edu> Message-ID: <43593977.6090307@snf.stanford.edu> Hi Tim -- Yes, laptops are acceptable. As are cell phones and PDA's. This appears in our Lab Manuals. (Laptops to have fans, which aren't really conducive to a good cleanroom environment, but we also have a lot of fans on equipment in the lab -- presumably, people aren't aiming the fans at their wafers.) Mary Tim Holme wrote: >I have a question about acceptability of materials entering into SNF. I >have seen several labmembers bring in laptops--are they acceptable? > >Thanks. > >Tim Holme >Prinz Group >Stanford University > > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From edmyers at stanford.edu Tue Oct 25 08:46:52 2005 From: edmyers at stanford.edu (Ed Myers) Date: Tue, 25 Oct 2005 08:46:52 -0700 Subject: SpecMat Logsheet 10/25/05 Message-ID: <6.2.1.2.2.20051025084540.04898a00@edmyers.pobox.stanford.edu> SpecMat Members, Looks like we need to hold our meeting today. Prof. Nishi has trumped CIS101, so I've booked CIS201 for 1:30 to 2:00 today. Regards, From edmyers at stanford.edu Tue Oct 25 10:37:06 2005 From: edmyers at stanford.edu (Ed Myers) Date: Tue, 25 Oct 2005 10:37:06 -0700 Subject: Fwd: Re: SpecMat Logsheet 10/25/05 Message-ID: <6.2.1.2.2.20051025103634.046931c0@edmyers.pobox.stanford.edu> >X-Sieve: CMU Sieve 2.2 >X-Mailer: QUALCOMM Windows Eudora Version 6.2.1.2 >Date: Tue, 25 Oct 2005 10:06:36 -0700 >To: Ed Myers >From: Paul Rissman >Subject: Re: SpecMat Logsheet 10/25/05 > >by the way, there was no attachment if you meant to send one > >At 08:46 AM 10/25/2005, you wrote: >>SpecMat Members, >> >>Looks like we need to hold our meeting today. Prof. Nishi has trumped >>CIS101, so I've booked CIS201 for 1:30 to 2:00 today. >> >>Regards, -------------- next part -------------- A non-text attachment was scrubbed... Name: SpecMat Logsheet.xls Type: application/octet-stream Size: 115712 bytes Desc: not available URL: From bipin at stanford.edu Tue Oct 25 23:08:33 2005 From: bipin at stanford.edu (Bipin Rajendran) Date: Tue, 25 Oct 2005 23:08:33 -0700 Subject: Permission to run a low temperature process Message-ID: <014f01c5d9f3$b2685730$0c9a0c80@supernova> Dear SpecMat members, I am planning to do a modified low temperature CMOS run on a 3D wafer. The details of the experiment are below. Start with Si wafer, that has Al metal wires, covered fully with thick LTO, which is CMPed at Cornell. Onto this wafer, I will bond and thin down an SOI wafer, thus creating my 'second device layer'. On this layer, I would like to make CMOS transistors with all processing temperatures below 450C, and laser annealing. I had got permission earlier to bring back my wafers after Laser annealing by doing a KOH decontamination clean. The list of equipments I would like to take my wafer to are below: Drytek2, AMT Etcher, P5000 etcher, TylanBPSG, TylanSiGe, Gasonics, Gryphon. I can do the different wafer cleans in WBSILICIDE, and avoid WBDIFF and WBNONMETAL. I would be very thankful if you can give me permission to do this run. Thanks Bipin -------------- next part -------------- An HTML attachment was scrubbed... URL: From bipin at stanford.edu Mon Oct 31 11:09:51 2005 From: bipin at stanford.edu (Bipin Rajendran) Date: Mon, 31 Oct 2005 11:09:51 -0800 Subject: Low Temperature Process for SOI CMOS Message-ID: <01ab01c5de4e$ac06cf70$fd6140ab@supernova> Dear SpecMat Members, I am attaching a detailed process flow of the Low Temperature CMOS fabrication steps. I will be happy to answer any further questions. Thanks Bipin -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: process03ver2a.pdf Type: application/pdf Size: 33219 bytes Desc: not available URL: From edmyers at stanford.edu Mon Oct 31 11:21:15 2005 From: edmyers at stanford.edu (Ed Myers) Date: Mon, 31 Oct 2005 11:21:15 -0800 Subject: Low Temperature Process for SOI CMOS In-Reply-To: <01ab01c5de4e$ac06cf70$fd6140ab@supernova> References: <01ab01c5de4e$ac06cf70$fd6140ab@supernova> Message-ID: <6.2.1.2.2.20051031111741.03f22320@edmyers.pobox.stanford.edu> SpecMat Members, Bipin is at my office asking questions about Cornell's CMP compatibility with our Clean equipment group. He is ready to send the wafers out and wants to make sure he can continue processing once they return. Also, he will be getting wafers thinned at Aptek Industries. Do we have any history with this company with regards to contamination? I head out on vacation on Wednesday and he is anxious to get a response. Please voice your opinions. Ed At 11:09 AM 10/31/2005, Bipin Rajendran wrote: >Dear SpecMat Members, >I am attaching a detailed process flow of the Low Temperature CMOS >fabrication steps. I will be happy to answer any further questions. >Thanks >Bipin From mtang at stanford.edu Mon Oct 31 11:58:10 2005 From: mtang at stanford.edu (Mary Tang) Date: Mon, 31 Oct 2005 11:58:10 -0800 Subject: Low Temperature Process for SOI CMOS In-Reply-To: <6.2.1.2.2.20051031111741.03f22320@edmyers.pobox.stanford.edu> References: <01ab01c5de4e$ac06cf70$fd6140ab@supernova> <6.2.1.2.2.20051031111741.03f22320@edmyers.pobox.stanford.edu> Message-ID: <1130788690.436677529d694@webmail.stanford.edu> Hi Ed -- I guess I'm less concerned with the CMP compatibility (since we take wafers from Berkeley and San Jose State CMP systems -- which are mixed use -- although we do require a physical scrubbing and decontamination clean before putting back into any clean systems) than the presence of Al wires that are underneath the LTO in his devices... Or did I misread his request? It seems to me that if there is Al present, we may not want any processing at wbsilicide, unless the pots are decontaminated afterward. Mary Quoting Ed Myers : > SpecMat Members, > > Bipin is at my office asking questions about Cornell's CMP compatibility > with our Clean equipment group. He is ready to send the wafers out and > wants to make sure he can continue processing once they return. Also, he > will be getting wafers thinned at Aptek Industries. Do we have any > history > with this company with regards to contamination? > > I head out on vacation on Wednesday and he is anxious to get a > response. Please voice your opinions. > > Ed > > > > At 11:09 AM 10/31/2005, Bipin Rajendran wrote: > >Dear SpecMat Members, > >I am attaching a detailed process flow of the Low Temperature CMOS > >fabrication steps. I will be happy to answer any further questions. > >Thanks > >Bipin > > > > From bipin at stanford.edu Mon Oct 31 14:05:15 2005 From: bipin at stanford.edu (Bipin Rajendran) Date: Mon, 31 Oct 2005 14:05:15 -0800 Subject: Low Temperature Process for SOI CMOS References: <01ab01c5de4e$ac06cf70$fd6140ab@supernova> <6.2.1.2.2.20051031111741.03f22320@edmyers.pobox.stanford.edu> <1130788690.436677529d694@webmail.stanford.edu> Message-ID: <025801c5de67$2ca58550$fd6140ab@supernova> Hi, In response to Mary's email, I have added a figure at the end of my process file, briefly showing what I intend to do. Hope that this will help. Thanks Bipin ----- Original Message ----- From: "Mary Tang" To: "Ed Myers" Cc: "Bipin Rajendran" ; ; Sent: Monday, October 31, 2005 11:58 AM Subject: Re: Low Temperature Process for SOI CMOS > Hi Ed -- > > I guess I'm less concerned with the CMP compatibility (since we take > wafers > from Berkeley and San Jose State CMP systems -- which are mixed use -- > although we do require a physical scrubbing and decontamination clean > before putting back into any clean systems) than the presence of Al wires > that are underneath the LTO in his devices... Or did I misread his > request? > > It seems to me that if there is Al present, we may not want any processing > at wbsilicide, unless the pots are decontaminated afterward. > > Mary > > Quoting Ed Myers : > >> SpecMat Members, >> >> Bipin is at my office asking questions about Cornell's CMP compatibility >> with our Clean equipment group. He is ready to send the wafers out and >> wants to make sure he can continue processing once they return. Also, he >> will be getting wafers thinned at Aptek Industries. Do we have any >> history >> with this company with regards to contamination? >> >> I head out on vacation on Wednesday and he is anxious to get a >> response. Please voice your opinions. >> >> Ed >> >> >> >> At 11:09 AM 10/31/2005, Bipin Rajendran wrote: >> >Dear SpecMat Members, >> >I am attaching a detailed process flow of the Low Temperature CMOS >> >fabrication steps. I will be happy to answer any further questions. >> >Thanks >> >Bipin >> >> >> >> > > -------------- next part -------------- A non-text attachment was scrubbed... Name: process03ver2a.pdf Type: application/pdf Size: 34494 bytes Desc: not available URL: