Permission to run a low temperature process
bipin at stanford.edu
Tue Oct 25 23:08:33 PDT 2005
Dear SpecMat members,
I am planning to do a modified low temperature CMOS run on a 3D wafer. The details of the experiment are below.
Start with Si wafer, that has Al metal wires, covered fully with thick LTO, which is CMPed at Cornell.
Onto this wafer, I will bond and thin down an SOI wafer, thus creating my 'second device layer'.
On this layer, I would like to make CMOS transistors with all processing temperatures below 450C, and laser annealing. I had got permission earlier to bring back my wafers after Laser annealing by doing a KOH decontamination clean.
The list of equipments I would like to take my wafer to are below:
Drytek2, AMT Etcher, P5000 etcher, TylanBPSG, TylanSiGe, Gasonics, Gryphon.
I can do the different wafer cleans in WBSILICIDE, and avoid WBDIFF and WBNONMETAL.
I would be very thankful if you can give me permission to do this run.
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