Low Temperature Process for SOI CMOS

Bipin Rajendran bipin at stanford.edu
Mon Oct 31 11:09:51 PST 2005

Dear SpecMat Members,
I am attaching a detailed process flow of the Low Temperature CMOS fabrication steps. I will be happy to answer any further questions.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://snf.stanford.edu/pipermail/specmat/attachments/20051031/65c487d3/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: process03ver2a.pdf
Type: application/pdf
Size: 33219 bytes
Desc: not available
URL: <http://snf.stanford.edu/pipermail/specmat/attachments/20051031/65c487d3/attachment.pdf>

More information about the specmat mailing list