Low Temperature Process for SOI CMOS

Mary Tang mtang at stanford.edu
Mon Oct 31 11:58:10 PST 2005


Hi Ed --

I guess I'm less concerned with the CMP compatibility (since we take wafers
from Berkeley and San Jose State CMP systems -- which are mixed use --
although we do require a physical scrubbing and decontamination clean
before putting back into any clean systems) than the presence of Al wires
that are underneath the LTO in his devices...  Or did I misread his
request?

It seems to me that if there is Al present, we may not want any processing
at wbsilicide, unless the pots are decontaminated afterward.

Mary

Quoting Ed Myers <edmyers at stanford.edu>:

> SpecMat Members,
>
> Bipin is at my office asking questions about Cornell's CMP compatibility
> with our Clean equipment group.  He is ready to send the wafers out and
> wants to make sure he can continue processing once they return.  Also, he
> will be getting wafers thinned at Aptek Industries.  Do we have any
> history
> with this company with regards to contamination?
>
> I head out on vacation on Wednesday and he is anxious to get a
> response.  Please voice your opinions.
>
> Ed
>
>
>
> At 11:09 AM 10/31/2005, Bipin Rajendran wrote:
> >Dear SpecMat Members,
> >I am attaching a detailed process flow of the Low Temperature CMOS
> >fabrication steps. I will be happy to answer any further questions.
> >Thanks
> >Bipin
>
>
>
>





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