Request for allowing poly and annealing process of wafers with CMOS compatible Si3N4 from outside Stanford CIS

Zheng, Jun F jun.f.zheng at intel.com
Fri Sep 30 10:47:21 PDT 2005


Sept. 30, 2005

 

To: Member of Special Materials Committee

 

From: Jun-Fei Zheng

 

Sub: Processing of Poly deposition on wafers received Si3N4 film from
outside CIS

 

We are evaluating Jet Vapor Deposited (JVD) Si3N4 film at Yale
University for certain applications. The process is CMOS compatible in a
custom built machine and wafers of 8" and 12" has been cross processed
for CMOS application with several major semiconductor companies,
including Intel.  To illustared the details, the materials involved in
the process are quartz, Teflon, and CMOS quality gas sources. JVD Si3N4
was process by mixture of SiH4 and Nitrogen gas in remote plasma through
a quartz inner nozzle with He gas as carrying gas in an outer nozzle.
The process is conducted at room temperature, which future reduce risk
of high temperature diffusion induced contamination. We have tested the
film contamination level by VPD (vapor phase decomposition) and all the
metallic contents are below detecting limit or less than 10e^10/cm2, the
criteria that we take such wafers into diffusion and poly furnace at
Intel development line for further process without concerning the
contamination based on the contamination test results. We only processed
the wafer through SC1 and SC2 bath as precaution measure before inserted
into Intel line.



We are requesting to allow the same materials to be processed in CIS for
in-situ poly deposition and annealing furnace. We want to run this at
CIS because we need in-situ poly deposition capability. In order to fit
the 6" tube or 4" tube, the 8" wafer has been notch cut and cleaned into
half, with the short dimension of 4", so that can be inserted into 6" or
4" tube.

 

We sincerely hope our request can be granted. We also wanted to avoid
H2SO4:H2O2 process as our wafer has never been through Lithographic
process and this is what the H2SO4:H2O2 mainly for but H2SO4:H2O2
process might destroy the gate quality Si3N4. We also do not see the
need for 50:1 HF dip, which is used for clear oxide formed on Silicon
during H2SO4:H2O2 process. We believe SC1 and SC2 in combination would
be able to address potential contamination during wafer handling and
shipping.

 

If you have any suggestion and question, please reply to my e-mail or
contact me at (408)921-8763 (cell).

 

Sincerely,

 

Jun-Fei Zheng

Senior Staff Scientist

Intel Corporation

Strategic Technology Group

SC1-05

3065 Bower Ave

Santa Clara, CA 95052

 

 

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