SpecMat Logsheet, 4/10/06
edmyers at stanford.edu
Tue Apr 18 16:52:18 PDT 2006
Access to the pquest and rtagaas was part of the request (see below). The
way I read his process flow, he will be etching PECVD oxide in the pquest
stopping on the GaN (maybe we should suggest drytek4 instead). When I
looked at the process flow, it seemed OK since they are staying away from
our clean and semiclean equipment. What is not know, it the area of GaN
which will be exposed by the oxide etch. It also seems strange they are
capping the etched area with another oxide.
5. Process Flow.
(1) RF sputtering in metallica, thickness: ~ 0.1 um
(2) Deposit 0.02-um SiO2 in sts PECVD
(3) Optical lithography in nikon, using 3612 photoresist
(4) Photoresist descum in drytek4
(5) Dry etch in pquest
(6) Photoresist removal in matrix
(7) Clean in PRS-1000 (heated to 40 C) in wbgaas
(8) Deposit 0.1-um SiO2 in sts PECVD
(9) Heating to 800 C for 1 second in rtagaas
(10) Cut the Silicon substrate using wafersaw. The GaN has already been
etch into 1-um wide and 10-um long stripes and covered with SiO2. With
visible marks etched on the wafer, the wafersaw blade will only cut into
the Silicon substrate without contacting or exposing any GaN.
At 05:00 PM 4/17/2006, Mary Tang wrote:
>Hey Ed and other specmat'ers --
>Jia Feng was just in my office asking about his GaN request. It looks
>like he's ordered (with Peter Griffin) some 2" targets which they plan to
>use on the sputter tool in Nishi's lab, not metalica, after all.
>However, the other part of his request was for etching GaN in pquest and
>after a few other steps, including an RTA in rtagaas.
>I've referred him back to you, because I'm not sure where the GaAs
>community stands on etching GaN (on silicon) in the pquest (is it
>considered part of the "GaAs process family" or the "silicon and
>everything else" family?) I'm also not sure about heating GaN in an RTA
>(although Jia mentions that they plan to step up the temperature in
>stages, gradually -- besides, the GaN film is capped with sts pecvd film
>at this point, so this may not be a problem.) His email of 3/22 outlines
>his process request.
>What do you all think?
>Ed Myers wrote:
>>This week is a light week for request. Honoring one of our members
>>requests, there is not meeting this week. I've outlined approaches for
>>each open item. If I don't hear from you by week's end, I will assume
>>the proposals are accepted.
>>1) PVDF (Polyvinylidene fluoride) allowed in the clean equipment.
>>The user is now looking at using ZnO (with options for PVDF and AlN).
>>Working with the user, he is still developing his process flow. I think
>>we have a SemiClean / Gold process flow which works, except for DRIE at
>>the end of his processing.
>>Recommendation: If he is not etching the piezoelectric materials to
>>allow him in STSetch for his through wafer etch at the end of his process.
>>2) GaN RF deposition in Metalica
>>The concern arises from the tendency of this material to generate ammonia
>>gas when exposed to humidity. I'm concerned we will pick up odor
>>complaints from metalica users. Also the discoloration of the internal
>>hardware is what called attention to the deposition in the first place.
>>Recommendation: Allow the deposition with the following restrictions.
>>A) The RF circuitry needs to be inspected to insure the safety
>>modifications are functioning.
>>B) Staff needs to be informed before each deposition
>>C) Need to use the RF chamber hardware and not the general use hardware.
>>3) NR9G-1000PY Resist: The primary hazard is cyclohexanone
>>Recommendation: Approve with all the safeguards of cyclohexanone resists
>>the user is familiar with.
>>4) TaN using DRYTEK 2:
>>5) Spin-on Dopant (B-150) on the Headway
>>Recommendation: Depending on the MSDS approve for the headway and tylan4
>Mary X. Tang, Ph.D.
>Stanford Nanofabrication Facility
>CIS Room 136, Mail Code 4070
>Stanford, CA 94305
>mtang at stanford.edu
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