PDMS face down in stsetch?

Mary Tang mtang at stanford.edu
Fri Apr 28 14:12:02 PDT 2006


Hi Alissa --

Can you tell us how thick your PDMS and oxide are?  And how thick is 
your Si?  (I'm presuming you are doing a through-wafer etch?)  And I'm 
curious...  how critical is your etch in terms of etch bias and 
profile?  I ask, because the XeF2 etcher has just arrived and Ed is 
hoping to have a functional process perhaps as early as next week.  If 
you can tolerate a somewhat isotropic Si etch, but with exquisite 
selectivity, this might be a good way to avoid resist burning and 
questions about contamination level (PDMS has a lot of metal ions, 
primarily Pt.) Please ask Ed about this.

By the way, my two cents' (but I'm no STS expert) is that you should use 
the holder, if only because PDMS like to stick (like Colorforms, 
remember them?) to smooth surfaces.

M

Alissa M. Fitzgerald wrote:

> Hi Specmat,
>  
> We have some wafers with a layer of PDMS over patterned Al, over 
> thermal oxide.  We would like to backside etch these wafers using 
> STSetch and stop on the thermal oxide.
>  
> Is it ok to put PDMS face down in the stsetch?  Would we need to use 
> the holder?
>  
> How hot does the chuck get? Are we likely to see resist burning 
> because the PDMS is a thermal insulator?
>  
> Please let us know as soon as you can, we might want to try some 
> experiments this weekend.
>  
> Thanks,
> Alissa



-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu





More information about the specmat mailing list