doped Silicon and Vanadium targets for SCT
ratiug at stanford.edu
Thu Jun 22 18:44:05 PDT 2006
We would like to request the approval to use Si and Vanadium sputtering targets in SCT.
We plan to use B-doped Si target (99.999%) from Williams Advanced Materials and Vanadium target (99.8%) from Plasmaterials.
The process flow is as follows:
1. Diffusion clean of Si wafers in wet bench diffusion
2. 6~20nm oxide growth in tylan furnace
3. Metal deposition in SCT
for Si, we plan to deposit 100-200nm thick
for V, we plan to deposit 50nm thick
4. Yes oven single
5. 3612 resist coating in SVG coater
6. Exposure in Karlsuss or Ultratech
7. Resist development in SVG developer
8. Metal etch:
for Si, dry etch process in Drytek2 (standard Si etch recipe)
for V, wet etch process in Wetbench General using self-owned clean beakers ( HF: HNO3:H2O=1:1:1 @RT )
9. Resist stripping in Wetbench General using self-owned clean beakers (PRX127, @40 degree C, 20 mins)
10. Forming gas annealing @ 400C for 30min in tylanfga
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