From mtang at stanford.edu Wed Aug 1 15:43:27 2007 From: mtang at stanford.edu (Mary Tang) Date: Wed, 01 Aug 2007 15:43:27 -0700 Subject: GaN as a clean material? Message-ID: <46B10C8F.6040108@stanford.edu> Hi all -- Three engineers from Alpha & Omega Semiconductor would like to join the lab. They would like to use silicon substrates with a thin layer (3-5 microns) of GaN in clean tools in the lab (stsetch and epi). I believe they plan to get these substrates from Honeywell. What do you all think? Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mcvittie at cis.Stanford.EDU Wed Aug 1 16:42:48 2007 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Wed, 1 Aug 2007 16:42:48 -0700 (PDT) Subject: GaN as a clean material? In-Reply-To: <46B10C8F.6040108@stanford.edu> Message-ID: Mary, We should talk to some of the Harris students. I am sure they have experience working with GaN. I expect it will behave similar to sapphire. In the STS etcher the issue will be the sputter etch rate when the plasma contacts directly contacts it. I expect sputter rate to be pretty low. In epi the issue is how much does it discompose in H2 at the epi temperature. Jim On Wed, 1 Aug 2007, Mary Tang wrote: > Hi all -- > > Three engineers from Alpha & Omega Semiconductor would like to join the > lab. They would like to use silicon substrates with a thin layer (3-5 > microns) of GaN in clean tools in the lab (stsetch and epi). I believe > they plan to get these substrates from Honeywell. What do you all think? > > Mary > > -- -------------------------------------------------------------- Jim McVittie, Ph.D. Senior Research Scientist Allen Center for Integrated Systems Electrical Engineering Stanford University jmcvittie at stanford.edu Rm. 336, 330 Serra Mall Fax: (650) 723-4659 Stanford, CA 94305-4075 Tel: (650) 725-3640 From support at global-fab.com Thu Aug 2 01:29:22 2007 From: support at global-fab.com (David Lee) Date: Thu, 2 Aug 2007 04:29:22 -0400 (EDT) Subject: Global Fab Surplus Equipment 200mm Message-ID: <1101760439259.1101401002153.9044.6.280425D5@scheduler> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Global Fab Surplus ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Month Day, Year ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ G-Fab has the following equipment available to sell immediatly. If interested please contact us ASAP. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Available for immediate sale! AMAT Mira CMP [http://rs6.net/tn.jsp?t=85iuadcab.0.wlh6f5bab.jfe8jybab.9044&ts=S0268&p=http%3A%2F%2Fwww.global-fab.com%2F]We have the following equipment for sale immediatly. Each tool has been extremly well maintained and is in excellent condition. Please contact us right away if you have any interest. Please feel free to forward this email to anyone you feel may have an interest. We want to move them quickly and the first acceptable bid will get the tool. * Varian Kestrel 750 Implanter * Varian E500HP Implanter * AMAT Mira CMP * IPEC 372 CMP (2 available) * Gasonics Aura 3000 (2 available) GFab006001 AP&S FSI PIRANHA SCP AWP 6514 GFab006002 AP&S FSI PIRANHA SCP GFab006003 Applied Materials MMTi Dep 3 Chamber Applied Materials ENDURA 5500 GFab006004 Applied Materials MMTi Dep, 4 Chamber Applied Materials ENDURA 5500 GFab006005 Applied Materials Metal 2 Dep, 5 Chamber Applied Materials ENDURA 5500 GFab006006 AXCELI Asher AXCELIS (GPL220 IP ) GFab006007 Canon SCANNER Canon ES2+ GFab006008 DNS Dai Nippon Screen SCRUBBER DNS Dai Nippon Screen SSW 80A GFab006009 DNS Dai Nippon Screen SCRUBBER DNS Dai Nippon Screen SSW 80A GFab006010 DNS Dai Nippon Screen SCRUBBER DNS Dai Nippon Screen SSW 80A-AR GFab006011 DNS Dai Nippon Screen SCRUBBER DNS Dai Nippon Screen SSW 80A GFab006012 DNS Dai Nippon Screen SC1 HF CLN DNS Dai Nippon Screen WS820C GFab006013 DNS Dai Nippon Screen BOE DNS Dai Nippon Screen WSW-2061 GFab006014 DNS Dai Nippon Screen SC1 HF CLN DNS Dai Nippon Screen WS820C GFab006015 DNS Dai Nippon Screen SC1 HF CLN DNS Dai Nippon Screen WS820L GFab006016 KLA-Tencor Thickness Measurement KLA Tencor UV1050 GFab006017 KLA-Tencor DEFECT INSPECTION KLA ES20XP GFab006018 TEL Tokyo Electron AP furnace Alpha 801 GFab006019 TEL Tokyo Electron AP furnace Alpha 801 GFab006020 TEL Tokyo Electron AP furnace Alpha 801 GFab006021 TEL Tokyo Electron SC1 CLN TEL Tokyo Electron UW8000 GFab006022 TEL Tokyo Electron ADD SC1 TEL Tokyo Electron UW8000 GFab006023 TEL Tokyo Electron WAPM TEL Tokyo Electron UW200Z ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Thank you for your time. Please email or call us for full detailed specs and pictures of these tools. Sincerely, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ David Lee 719-686-0128 support at global-fab.com Chris Detrick 805-215-9188 chris.detrick at global-fab.com Global Fab Surplus www.global-fab.com ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Forward email http://ui.constantcontact.com/sa/fwtf.jsp?m=1101401002153&ea=specmat at snf.stanford.edu&a=1101760439259 This email was sent to specmat at snf.stanford.edu, by support at global-fab.com Update Profile/Email Address http://visitor.constantcontact.com/d.jsp?p=oo&m=1101401002153&ea=specmat%40snf.stanford.edu&se=9044&t=1101760439259&lang=en&reason=F Instant removal with SafeUnsubscribe(TM) http://visitor.constantcontact.com/d.jsp?p=un&m=1101401002153&ea=specmat%40snf.stanford.edu&se=9044&t=1101760439259&lang=en&reason=F Privacy Policy: http://ui.constantcontact.com/roving/CCPrivacyPolicy.jsp Global Fab Surplus | 195 Kirkstone Lane | Colorado Springs | CO | 80906 -------------- next part -------------- An HTML attachment was scrubbed... URL: From newsletter at nilt.com Thu Aug 2 13:42:29 2007 From: newsletter at nilt.com (newsletter at nilt.com) Date: Thu, 2 Aug 2007 22:42:29 +0200 Subject: NILT nanonews august 3: Discovery of hidden quantum order, graphene sniffs dangerous molecules, CNTs aim for cheap touch screens Message-ID: An HTML attachment was scrubbed... URL: From info at fabsurplus.com Thu Aug 2 17:40:34 2007 From: info at fabsurplus.com (SDI Semiconductor Instruments) Date: Fri, 3 Aug 2007 02:40:34 +0200 (CEST) Subject: Partial 6 inch line for sale by fabsurplus.com Message-ID: <24912270.1186102376331.JavaMail.root@server1.sdi-fabsurplus.com> Dear Sir or Madam, SDI Group is proud to present the following partial 6 inch line available now as detailed below. Sealed bids on these 77 individual tools and for the complete tool set will be accepted no later than August 25, 2007. SDI may, at its sole discretion, accept bids received beyond this date. Bids will be opened the week of September 3, 2007. Potential Buyers may, with a minimum of 48 hours advance notice, schedule an inspection tour of tools. Buyer should detail tools of interest prior to the tour. . All tools are sold ?As Is ? Where Is?. Payment in full is expected 72 hours after bid acceptance. Buyer assumes all cost for disconnection, rigging and crating/packaging of purchased tools Tool removals will be scheduled by SDI to minimize negative effects to Fab operations. Tools located inside Fab will be disconnected by approved contractors only. Tools located inside Fab will be removed by approved riggers only. Tools will be crated and packaged by approved companies only. To see details of each item, please refer to the embedded link appearing below. We look forwards to receiving your best offers as soon as possible. http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16094 AG Associates 4108 RTP http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16095 AG Associates 4100S RTP http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16083 Applied Materials P5000 MARK I frame, 3 Nitride/PSG PECVD chambers 1 etchback chamber, AMT0 heat exchanger, DPA on 3 dep chambers Gasses (PH3,NF3,NH3,SiH4, CF4, Ar & N2O) http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16084 Applied Materials P5000 MARK I frame, 3 Nitride/PSG PECVD chambers 1 etchback chamber, AMT0 heat exchanger, DPA on 3 dep chambers Gasses (PH3,NF3,NH3,SiH4, CF4, Ar & N2O) http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16085 Applied Materials P5000 MARK II frame, 3 Nitride/PSG PECVD chambers 1 etchback chamber, AMT0 heat exchanger, DPA on 3 dep chambers Gasses (PH3,NF3,NH3,SiH4, CF4, Ar & N2O) http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16096 Applied Materials P5000 Mark II frame, 3 BPTEOS Universal & 1 etchback, 150mm Chambers AMT0 heat exchanger, Version 4 hot box( No Ampules) Gasses ( C2F6, O2,NF3, TEOS, TMP, TMB & He) http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16113 Applied Materials P5000 Mark II frame, 2 TEOS 2 etchback, 150mm Chambers AMT0 heat exchanger, Version 4 hot box( No Ampules) Gasses ( C2F6, O2,NF3,TEOS, & He) http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16118 Applied Materials P5000 Mark II frame, 3 TEOS 1 etchback, 150mm Chambers AMT0 heat exchanger, Version 4 hot box9 No Ampules) Gasses ( C2F6, O2,NF3,TEOS, & He) http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16139 Applied Materials 7810RP EPI REACTOR http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16145 Applied Materials P5000 Mark II frame, 2 TEOS Universal & 2 etchback, 150mm Chambers AMT0 heat exchanger, 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http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16153 Telos H2M Multipoint Hydrogen monitor http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16150 Thermawave 400XP IMPLANT DOPANT MEASUREMENT http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16086 Thermco 4 stack HORIZONTAL FURNACE http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16087 Thermco 4 stack HORIZONTAL FURNACE http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16088 Thermco 4 stack HORIZONTAL FURNACE http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16089 Thermco 4 stack HORIZONTAL FURNACE http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16090 Thermco 4 stack HORIZONTAL FURNACE http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16091 Thermco 4 stack HORIZONTAL FURNACE http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16092 Thermco 4 stack HORIZONTAL FURNACE http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16137 Ultratech 1000 1:1 Wide field stepper Intellegent autoloader http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16138 Ultratech 1000 EPI REACTOR http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16117 Varian 3290 Conmag PVD SYSTEM http://www.sdi-fabsurplus.com/sdi_catalog/salesItemDetails.do?id=16093 Westek 472 CMP POLISHER Yours sincerely, Stephen Howe SDI Semiconductor Instruments Srl Napoli 80123 Italy Mobile: Italy (39) 335 710 7756 Fax Italy (39) 066 051 3344 info at fabsurplus.com Skype: Stephencshowe http://www.fabsurplus.com A MEMBER OF SEMI Vito Vigliotti SDI Semiconductor Instruments Srl Napoli 80123 Italy Mobile: Italy (39) 331 5763012 Fax Italy (39) 066 051 3344 vito at fabsurplus.com Oliver Dunne SDI Semiconductor Instruments Ireland Limited 20, Newtown Abbey Trim, Co. Meath, Ireland Tel: Ireland (353) 4694 37097 Mobile: Ireland (353) 872 985 561 ollie.dunne at fabsurplus.com Skype: sdiireland Michael Fortune SDI Semiconductor Instruments Ireland Limited 7, Friarspark, Trim, Co. Meath, Ireland Tel: Ireland (353) 4694 37111 Mobile: Ireland (353) 879150198 Mike Murehead SDI Fabsurplus LLC Georgetown, TX 78628 Tel: 512-635-8027 Fax: 801-217-6104 mike at fabsurplus.com Skype: sditexas Randall Copeland SDI Fabsurplus LLC Beaverton, Oregon Tel: (503) 523-8795 Fax: (801) 217-6104 support at fabsurplus.com Contact us now to buy and sell used equipment and enjoy the benefits of cost-saving. This message may be considered an advertisement or solicitation. If you would like to opt-out of receiving future commercial email marketing messages from SDI Group , Please reply to this message with the word "remove" in the subject line.If you reply from an e-mail address different from the one you wish to unsubscribe, please send us also the e-mail address you wish to unsubscribe. From jkoma at stanford.edu Tue Aug 7 13:51:14 2007 From: jkoma at stanford.edu (Jason Komadina) Date: Tue, 07 Aug 2007 13:51:14 -0700 Subject: PDMS in Innotec Message-ID: <46B8DB42.50205@stanford.edu> I need to deposit metal on PDMS (polydimethylsiloxane). The PDMS layer is deposited on gold-coated Si wafers in the MERL clean shop and will be transported to SNF in wafer cases wrapped in foil and in a ziploc bag. Is it acceptable to use Innotec for this? I am not trained on the other metallization tools in the SNF. The deposition can be masked by either a kapton shadow mask or stainless steel shadow mask. Thanks, Jason Komadina From mtang at stanford.edu Tue Aug 7 15:46:57 2007 From: mtang at stanford.edu (Mary Tang) Date: Tue, 07 Aug 2007 15:46:57 -0700 Subject: PDMS in Innotec In-Reply-To: <46B8DB42.50205@stanford.edu> References: <46B8DB42.50205@stanford.edu> Message-ID: <46B8F661.8000202@stanford.edu> Hi all -- I believe this has been approved through SpecMat previously. Neville Mehenti was doing this (either through innotec or metallica) and a couple other people as well. The PDMS should be fully cured (i.e., not tacky/liquid). The only concern would be if the metal peeled off the PDMS while in the system -- this could happen if the substrate got too warm, as the thermal expansion coefficient of PDMS is pretty high. This is less of an issue if the PDMS is thin and spun/cured onto substrates (doesn't expand much if constrained.) Mary Jason Komadina wrote: > I need to deposit metal on PDMS (polydimethylsiloxane). The PDMS layer > is deposited on gold-coated Si wafers in the MERL clean shop and will > be transported to SNF in wafer cases wrapped in foil and in a ziploc > bag. Is it acceptable to use Innotec for this? I am not trained on the > other metallization tools in the SNF. The deposition can be masked by > either a kapton shadow mask or stainless steel shadow mask. > > Thanks, > Jason Komadina -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From newsletter at nilt.com Thu Aug 9 14:28:06 2007 From: newsletter at nilt.com (newsletter at nilt.com) Date: Thu, 9 Aug 2007 23:28:06 +0200 Subject: NILT nanonews august 10: Scientists train nano building blocks to take on new shapes, organic solar cells gain ground, glue that can be turned on and off Message-ID: <6875946aaa1e333297c0caac00163ea2@nilt.com> An HTML attachment was scrubbed... URL: From newsletter at discount-educational-software.com Tue Aug 14 16:42:22 2007 From: newsletter at discount-educational-software.com (Educational Software Newsletter) Date: Tue, 14 Aug 2007 19:42:22 -0400 Subject: Educational Software Sale - August 2007 Message-ID: Computer Products for Eduation is pleased to provide Educational Software News to qualified students, faculty, staff, and schools for current news on pricing and availability of Academic Edition Software from Microsoft, Adobe, Corel, Autodesk, Quark, EndNote, FileMaker, and many other major software manufacturers. Back-to-School Season is here and Microsoft and Adobe are ready to help you get the most out of your back-to-school budget. The Adobe CS3 Master Collection and Production Premium suites are now shipping along with the four other CS3 suites - each suite containing different sets of the new CS3 products. All Adobe CS3 products are available in both Macintosh and Windows versions. Microsoft Windows Vista Premium along with the new Office 2007 products are also great tools for helping you get the most out the upcoming school year! Please view our website for more information: http://www.discount-educational-software.com or call 800-679-7007. Educational software is exclusively available to qualified Students, Teachers, Faculty, Staff, and Schools of Higher Education and K-12 institutions.(see below for details) ------ Education Prices for August 2007 -------- ---------------------- Education Standard You ADOBE Price Retail Save! ---------------------- --------- ------ ----- Acrobat 8.0 Professional $148.95 $500 70% Acrobat 8.0 Standard $96.95 $300 68% After Effects CS3 $348.95 $999 65% Contribute CS3 $84.95 $149 43% CS3 Design Premium (1) $589.95 $1799 67% CS3 Design Standard (2) $389.95 $1199 67% CS3 Master Collection(3) $989.95 $2499 60% CS3 Production Premium (4) $589.95 $1699 65% CS3 Web Premium (5) $489.95 $1599 69% CS3 Web Standard (6) $389.95 $999 61% Dreamweaver CS3 $198.95 $399 50% Fireworks CS3 $98.95 $299 67% Flash Pro CS3 $248.95 $699 64% Flex Builder 2.0 $92.95 $749 88% Illustrator CS3 $198.95 $699 72% InDesign CS3 $198.95 $699 72% PageMaker 7.0.2 $339.95 $499 32% Photoshop Elements 5.0 $68.95 $100 31% Photoshop Extended CS3 $298.95 $999 70% Premiere Elements 3.0 $67.95 $100 32% Premiere Pro CS3 $348.95 $799 56% Soundbooth CS3 $98.95 $199 50% (1) CS3 Design Premium includes: InDesign, Photoshop Extended, Illustrator, Flash Pro, Dreamweaver, and Acrobat 8 Pro (2) CS3 Design Standard includes: InDesign, Photoshop, Illustrator, and Acrobat 8 Pro (3) CS3 Master Collection includes: InDesign, Photoshop Extended, Illustrator, Flash Pro, Dreamweaver, Contribute, Fireworks, After Effects Pro, Premiere Pro, Soundbooth, Encore, OnLocation, Ultra, and Acrobat 8 Pro (4) CS3 Production Premium includes: Photoshop Extended, Illustrator, Flash Pro, After Effects Pro, Premiere Pro, Encore, OnLocation, and Ultra (5) CS3 Web Pemium includes: Photoshop Extended, Illustrator, Acrobat 8 Pro, Flash Pro, Dreamweaver, Contribute, and Fireworks (6) CS3 Web Standard includes: Flash Pro, Dreamweaver, Contribute, and Fireworks http://www.discount-educational-software.com ---------------------- Education Standard You MICROSOFT Price Retail Save! ---------------------- --------- ------ ----- Excel 2007 $115.95 $229 49% Expressions Web 1.0 $59.95 $299 80% Office 2004 Macintosh $148.95 $500 70% Office 2007 Professional(2) $189.95 $499 62% Office 2007 Standard(1) $148.95 $399 63% Office 2007 Ultimate(3) $259.95 $679 62% Office Accounting Pro 2007 $89.95 $229 61% OneNote 2007 $48.95 $100 51% Powerpoint 2007 $118.95 $229 48% Project 2007 Professional $198.95 $999 80% Project 2007 Standard $69.95 $349 80% Publisher 2007 $98.95 $169 41% Visio 2007 Professional $159.95 $559 71% Visio 2007 Standard $84.95 $259 67% Visual Studio 2005 Professional $109.95 $809 86% Visual Studio 2005 Standard $59.95 $299 80% Windows Vista Home Premium Upg $69.95 $160 56% Windows XP Professional Upgrade $94.95 $200 53% (1)Office 2007 Standard includes: Word, Excel, PowerPoint, Outlook. (2)Office 2007 Professional includes: Word, Excel, PowerPoint, Outlook, Access, Publisher. (3)Office 2007 Ultimate includes: Word, Excel, PowerPoint, Outlook, Access, Publisher, Groove, InfoPath. http://www.discount-educational-software.com ---------------------- Education Standard You AUTODESK Price Retail Save! ---------------------- --------- ------ ----- 3ds Max 9 $389.95 $3495 89% Architecture 2008 $379.95 $4995 92% AutoCAD 2008 $379.95 $3750 90% AutoCAD LT 2008 $148.95 $899 83% Civil 3D 2008 $469.95 $4995 91% Inventor Professional 2008 $479.95 $4995 90% Map 3D 2008 $469.95 $4995 91% Raster Design 2008 $148.95 $2095 93% Revit Architecture Suite 2008 $469.95 $4995 91% Revit MEP Suite 2008 $469.95 $4995 91% Revit Structure Suite 2008 $469.95 $4995 91% Viz 2008 $289.95 $1995 85% The above Autodesk prices are for Students, Teachers, Faculty, & Staff for personal use only. Pricing for schools for institutional/class-room lab use is different. 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Purchase Orders may be faxed from schools to: 800-679-6996. Educational Software has the exact same features and functionality as the full priced retail Commercial Full-Versions of the software. Visit our website to view thousands of other computer products and accessories available from CPE at similar discounts. All software products from CPE are authentic original software from the manufacturer. These are not pirated software copies. All software comes in original manufacturer's packaging and contains a valid verifiable license. ------------------------- Volume Licensing: ------------------------- For software licensing information for schools for quantities of five to ten (5-10) or more units of software, depending on the product, please call 800-679-7007 for complete infomation. ---------------------------------------- Qualified Educational Buyers: ---------------------------------------- The following are defined as Qualified Education Buyers. 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However, all prices and availability are subject to change without notice, due to factors outside our control. __________________________ We hope you have found this message valuable. However, if you do not wish to recieve any more newletters from CPE, please use the following link: http://www.discount-educational-software.com/rem.asp?a=remv&e=specmat at snf.stanford.edu Or call 800-679-7007 for additional options. __________________________ Sincerely, Computer Products for Education 5325 140th Avenue North Clearwater, Florida 33760 Tel: 800-679-7007 Fax: 800-679-6996 support at discount-educational-software.com ___________________ THANK YOU!!! From mtang at stanford.edu Wed Aug 15 11:35:46 2007 From: mtang at stanford.edu (Mary Tang) Date: Wed, 15 Aug 2007 11:35:46 -0700 Subject: [Fwd: Re: SNF Consultants] Message-ID: <46C34782.7070602@stanford.edu> Hi all -- What do you think? Teledyne's furnaces are down and they would like to find a consultant to do this processing for them. I asked for their processes and here they are. The tricky parts are that the wafers are 2" silicon carbide and contain Ti/Ni when they arrive. If there were a consultant willing, could this be done here? Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An embedded message was scrubbed... From: Emil M Hanna Subject: Re: SNF Consultants Date: Thu, 9 Aug 2007 10:43:25 -0700 Size: 181502 URL: From edmyers at stanford.edu Wed Aug 15 12:27:47 2007 From: edmyers at stanford.edu (Ed Myers) Date: Wed, 15 Aug 2007 12:27:47 -0700 Subject: [Fwd: Re: SNF Consultants] In-Reply-To: <46C34782.7070602@stanford.edu> References: <46C34782.7070602@stanford.edu> Message-ID: <6.2.5.6.2.20070815122339.03b930c0@stanford.edu> All, I was actually working on specmat items before lunch. I tried to find contamination levels in the wafers on the Cree website, but nothing was listed. Looking at their process flow, they do a number of RCA cleans at their facility. I think we should be OK if we label the substrates as SemiClean (Ti can be clean and our Ni is considered Semiclean). This will allow them in to LTO and Poly (we can always ask for capping layers) and we have enough oxide furnaces to match. Being SemiClean pushes the RCA cleans they want to do here, in to the silicide wet bench. As for consultants, I suggest Linda. This matches her tool set and processing choices very well. Ed At 11:35 AM 8/15/2007, Mary Tang wrote: >Hi all -- > >What do you think? Teledyne's furnaces are down and they would like >to find a consultant to do this processing for them. I asked for >their processes and here they are. The tricky parts are that the >wafers are 2" silicon carbide and contain Ti/Ni when they >arrive. If there were a consultant willing, could this be done here? > >Mary > >-- >Mary X. Tang, Ph.D. >Stanford Nanofabrication Facility >CIS Room 136, Mail Code 4070 >Stanford, CA 94305 >(650)723-9980 >mtang at stanford.edu >http://snf.stanford.edu > > > >Return-Path: >Received: from mx3.stanford.edu (mx3.Stanford.EDU [171.67.20.23]) > by pobox03.stanford.edu (Cyrus v2.3.7) with LMTPA; > Thu, 09 Aug 2007 10:43:30 -0700 >X-Sieve: CMU Sieve 2.3 >Received: by mx3.stanford.edu (Postfix) > id 27A964BE4A; Thu, 9 Aug 2007 10:43:30 -0700 (PDT) >Delivered-To: mtang at stanford.edu >Received: from mx3.stanford.edu (localhost.localdomain [127.0.0.1]) > by localhost (Postfix) with SMTP id 250374BE2C; > Thu, 9 Aug 2007 10:43:30 -0700 (PDT) >Received: from tdysmtp2.teledyne.com (tdysmtp2.teledyne.com [74.201.16.13]) > by mx3.stanford.edu (Postfix) with ESMTP id 9EBC54BDE5; > Thu, 9 Aug 2007 10:43:28 -0700 (PDT) >Received: from rsctonotes01.rwsc.com ([130.50.4.71]) > by tdysmtp2.teledyne.com (Lotus Domino Release 6.5.4 HF96) > with ESMTP id 2007080910432000-8594 ; > Thu, 9 Aug 2007 10:43:20 -0700 >In-Reply-To: <46B8EAA8.5020404 at stanford.edu> >Subject: Re: SNF Consultants >To: Mary Tang >Cc: Ed Myers , > Donald S Deakin , > Gabor Nagy , > Berinder Brar >X-Mailer: Lotus Notes Release 6.5.2 June 01, 2004 >Message-ID: > >From: Emil M Hanna >Date: Thu, 9 Aug 2007 10:43:25 -0700 >Return-Receipt-To: ehanna at teledyne.com >MIME-Version: 1.0 >X-MIMETrack: Serialize by Router on >RSCTONotes01/ThousandOaks/RSC/Rockwell(Release > 6.5.4FP2|September 12, 2005) at 08/09/2007 10:43:26 AM, > Itemize by SMTP Server on TDYSMTP2/Teledyne(Release 6.5.4 > HF96|May 02, 2005) at > 08/09/2007 10:43:20 AM, > Serialize by Router on TDYSMTP2/Teledyne(Release 6.5.4 > HF96|May 02, 2005) at > 08/09/2007 10:43:21 AM >Content-type: multipart/mixed; > Boundary="0__=07BBF9A1DFF280218f9e8a93df938690918c07BBF9A1DFF28021" >Content-Disposition: inline > > >Hi Mary, > >Attached please find two PDF files, the process outline and the services >needed. The Red text in the outline file indicates the furnace services >needed. Please take a look at it and let me know if you have any question. > >This is a 2" Silicon Carbide four wafer lot. > > >(See attached file: Process Outline.pdf)(See attached file: Furnace >service.pdf) > > > >Regards >Emil Hanna >PH: (805) 373.4346 >FAX: (805) 373.4869 >e-mail: ehanna at teledyne.com > > > > > > Mary Tang > du> To > ehanna at teledyne.com > 08/07/2007 02:56 cc > PM Ed Myers > Subject > SNF Consultants > > > > > > > > > > >Hi Emil -- > >Thanks for your interest in SNF! As discussed, you had mentioned that >you wanted to be able to deposit lto and poly on some 2" silicon carbide >substrates. The tools at SNF might be able to support this, provided >your substrates (you mentioned they were purchased from Cree and have >not undergone any other processing, is that correct?) are considered >CMOS or electronics grade. If you do not have a certificate for >elemental analysis (for heavy and alkali metals), then a TXRF analysis >from a reputable lab would also be acceptable. Please do describe any >processing (including cleans) that these wafers may have undergone after >acquiring them from your supplier. Please describe any parameter specs >you may have for the depositions and other processing. Also tell us >what thickness your substrates are. > >It is not likely that our staff can support your processing needs in the >time frame you require. However, we would recommend you consider >contacting one of the contractors/consultants listed on our website. >Please be aware that these contractors are not SNF employees and we make >no guarantees of their work. Any contract terms should be negotiated >directly with the contractor. Any user of the SNF lab will be billed >directly to a PO that you would provide -- the contractor will bill >his/her services separately. For a list of contractors, see: >http://snf.stanford.edu/Access/RemoteUsers/Contractors.html > >Thanks again for your interest -- please do get in touch if you have >further questions -- > >Best, > >Mary > >-- >Mary X. Tang, Ph.D. >Stanford Nanofabrication Facility >CIS Room 136, Mail Code 4070 >Stanford, CA 94305 >(650)723-9980 >mtang at stanford.edu >http://snf.stanford.edu > > > From nharjee at stanford.edu Wed Aug 15 21:08:51 2007 From: nharjee at stanford.edu (Nahid Harjee) Date: Wed, 15 Aug 2007 21:08:51 -0700 Subject: Proposal for non-standard process in stsetch Message-ID: <2feeb6700708152108r59c77b58jfdd7a489b4a24814@mail.gmail.com> SpecMat Committee, I am working with SOI wafers to build piezoresistive cantilevers. The interconnect on the cantilevers is a Cr/Au stack. To release the cantilevers, I am seeking permission to use stsetch to etch through the handle layer to the buried oxide, provided that the Cr/Au is fully encapsulated and is never exposed to the plasma. Below is the material stack I propose: Plasma (SF6/C4F8) Resist (7 um, patterned) Si (530 um handle layer) SiO2 (1 um buried oxide) Si (6 um device layer, patterned into cantilevers) SiO2 (100 nm) Cr (10 nm) Au (100 nm) Resist (15 um, unpatterned) Aluminum holder He cooling I believe that this process has been approved by SpecMat in the past. Please let me know if you have any questions/comments or would like more details about my process. I look forward to your response. Thanks, nh -- Nahid Harjee Ph.D. Candidate Electrical Engineering Stanford University 408-761-8651 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mcvittie at cis.Stanford.EDU Wed Aug 15 22:53:47 2007 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Wed, 15 Aug 2007 22:53:47 -0700 (PDT) Subject: Proposal for non-standard process in stsetch In-Reply-To: <2feeb6700708152108r59c77b58jfdd7a489b4a24814@mail.gmail.com> Message-ID: Hi, A few years back, a number of experiments were done to see if we could bury Au so that a Au contaminated wafer could be etched in the STS without exposing the plasma or the chuck to Au. At that time, all the attempts failed. We always detected Au on the surface. Part of the problem is that resist always picks up Au from the etch solution and then deposits it back on the wafer when the resist is stripped. Jim On Wed, 15 Aug 2007, Nahid Harjee wrote: > SpecMat Committee, > > I am working with SOI wafers to build piezoresistive cantilevers. The > interconnect on the cantilevers is a Cr/Au stack. To release the > cantilevers, I am seeking permission to use stsetch to etch through the > handle layer to the buried oxide, provided that the Cr/Au is fully > encapsulated and is never exposed to the plasma. Below is the material stack > I propose: > > Plasma (SF6/C4F8) > > Resist (7 um, patterned) > Si (530 um handle layer) > SiO2 (1 um buried oxide) > Si (6 um device layer, patterned into cantilevers) > SiO2 (100 nm) > Cr (10 nm) > Au (100 nm) > Resist (15 um, unpatterned) > Aluminum holder > > He cooling > > I believe that this process has been approved by SpecMat in the past. Please > let me know if you have any questions/comments or would like more details > about my process. I look forward to your response. > > Thanks, > > nh > > -- -------------------------------------------------------------- Jim McVittie, Ph.D. Senior Research Scientist Allen Center for Integrated Systems Electrical Engineering Stanford University jmcvittie at stanford.edu Rm. 336, 330 Serra Mall Fax: (650) 723-4659 Stanford, CA 94305-4075 Tel: (650) 725-3640 From mtang at stanford.edu Thu Aug 16 08:26:07 2007 From: mtang at stanford.edu (Mary Tang) Date: Thu, 16 Aug 2007 08:26:07 -0700 Subject: Proposal for non-standard process in stsetch In-Reply-To: References: Message-ID: <46C46C8F.6010405@stanford.edu> Hi Jim, et al -- Yes, I remember you mentioning these experiments... (By the way, would you still happen to have this data and be willing to share it? It seems to me that there was an awful lot of really useful information in it about etching, furnaces, and cleans.) Regarding Nahid's request.... as I vaguely recall from the last time this came up (pre-Beth Pruitt) the policy was to allow gold in the stsetch provided: 1. If the gold was patterned that it had been done by lift-off rather than etching 2. No gold exposed to plasma -- that it was completely covered with resist. The rationale was that gold is pretty inert in its noble metal state, but that contamination becomes an issue once wet etching is done and gold appears in various oxidation states which are soluble (and appear all over the wafer). It was agreed not to support Beth's request for Au in stsetch when she was a grad student because the above two conditions were not met, so she went to UCSB. I seem to recall (perhaps incorrectly) that the TXRF experiments were done on wafers in which the gold had been patterned using KI etchant, which would leave soluble gold atoms on the wafer surfaces to examine the worst case scenario of gold in stsetch.... Nahid is proposing to cover unpatterned gold present on the backside of the wafers with resist -- and to use the holder. It would seem that the cross-contamination risk should be low.... My two cents' Mary Jim McVittie wrote: > Hi, > > A few years back, a number of experiments were done to see if we could > bury Au so that a Au contaminated wafer could be etched in the STS without > exposing the plasma or the chuck to Au. At that time, all the attempts > failed. We always detected Au on the surface. Part of the problem is that > resist always picks up Au from the etch solution and then deposits it back > on the wafer when the resist is stripped. > > Jim > > On Wed, 15 Aug 2007, Nahid Harjee wrote: > > >> SpecMat Committee, >> >> I am working with SOI wafers to build piezoresistive cantilevers. The >> interconnect on the cantilevers is a Cr/Au stack. To release the >> cantilevers, I am seeking permission to use stsetch to etch through the >> handle layer to the buried oxide, provided that the Cr/Au is fully >> encapsulated and is never exposed to the plasma. Below is the material stack >> I propose: >> >> Plasma (SF6/C4F8) >> >> Resist (7 um, patterned) >> Si (530 um handle layer) >> SiO2 (1 um buried oxide) >> Si (6 um device layer, patterned into cantilevers) >> SiO2 (100 nm) >> Cr (10 nm) >> Au (100 nm) >> Resist (15 um, unpatterned) >> Aluminum holder >> >> He cooling >> >> I believe that this process has been approved by SpecMat in the past. Please >> let me know if you have any questions/comments or would like more details >> about my process. I look forward to your response. >> >> Thanks, >> >> nh >> >> >> > > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mcvittie at cis.Stanford.EDU Thu Aug 16 08:36:56 2007 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Thu, 16 Aug 2007 08:36:56 -0700 (PDT) Subject: Proposal for non-standard process in stsetch In-Reply-To: <46C46C8F.6010405@stanford.edu> Message-ID: Mary, I do not remember Au ever being allowed in the STS. As I said the experiment never proved one could really bury it. The proposed solution was to dedicate the old STS to Au wafers after the new STS was up. I agree that Au is pretty inert but it is a lifetime killed in Si. It is also a fast diffuser. Since we never test lifetime in the lab and it is an issue for only a few users, maybe we should stop worrying about Au and other metals. Jim On Thu, 16 Aug 2007, Mary Tang wrote: > Hi Jim, et al -- > > Yes, I remember you mentioning these experiments... (By the way, would > you still happen to have this data and be willing to share it? It seems > to me that there was an awful lot of really useful information in it > about etching, furnaces, and cleans.) > > Regarding Nahid's request.... as I vaguely recall from the last time > this came up (pre-Beth Pruitt) the policy was to allow gold in the > stsetch provided: > > 1. If the gold was patterned that it had been done by lift-off rather > than etching > 2. No gold exposed to plasma -- that it was completely covered with resist. > > The rationale was that gold is pretty inert in its noble metal state, > but that contamination becomes an issue once wet etching is done and > gold appears in various oxidation states which are soluble (and appear > all over the wafer). It was agreed not to support Beth's request for Au > in stsetch when she was a grad student because the above two conditions > were not met, so she went to UCSB. I seem to recall (perhaps > incorrectly) that the TXRF experiments were done on wafers in which the > gold had been patterned using KI etchant, which would leave soluble gold > atoms on the wafer surfaces to examine the worst case scenario of gold > in stsetch.... Nahid is proposing to cover unpatterned gold present on > the backside of the wafers with resist -- and to use the holder. It > would seem that the cross-contamination risk should be low.... > > My two cents' > > Mary > > Jim McVittie wrote: > > Hi, > > > > A few years back, a number of experiments were done to see if we could > > bury Au so that a Au contaminated wafer could be etched in the STS without > > exposing the plasma or the chuck to Au. At that time, all the attempts > > failed. We always detected Au on the surface. Part of the problem is that > > resist always picks up Au from the etch solution and then deposits it back > > on the wafer when the resist is stripped. > > > > Jim > > > > On Wed, 15 Aug 2007, Nahid Harjee wrote: > > > > > >> SpecMat Committee, > >> > >> I am working with SOI wafers to build piezoresistive cantilevers. The > >> interconnect on the cantilevers is a Cr/Au stack. To release the > >> cantilevers, I am seeking permission to use stsetch to etch through the > >> handle layer to the buried oxide, provided that the Cr/Au is fully > >> encapsulated and is never exposed to the plasma. Below is the material stack > >> I propose: > >> > >> Plasma (SF6/C4F8) > >> > >> Resist (7 um, patterned) > >> Si (530 um handle layer) > >> SiO2 (1 um buried oxide) > >> Si (6 um device layer, patterned into cantilevers) > >> SiO2 (100 nm) > >> Cr (10 nm) > >> Au (100 nm) > >> Resist (15 um, unpatterned) > >> Aluminum holder > >> > >> He cooling > >> > >> I believe that this process has been approved by SpecMat in the past. Please > >> let me know if you have any questions/comments or would like more details > >> about my process. I look forward to your response. > >> > >> Thanks, > >> > >> nh > >> > >> > >> > > > > > > > -- -------------------------------------------------------------- Jim McVittie, Ph.D. Senior Research Scientist Allen Center for Integrated Systems Electrical Engineering Stanford University jmcvittie at stanford.edu Rm. 336, 330 Serra Mall Fax: (650) 723-4659 Stanford, CA 94305-4075 Tel: (650) 725-3640 From newsletter at nilt.com Fri Aug 17 00:00:08 2007 From: newsletter at nilt.com (newsletter at nilt.com) Date: Fri, 17 Aug 2007 09:00:08 +0200 Subject: NILT nanonews august 17: Nanoparticle technique improves semiconductors, terabit disk media, nano resonators form tiny logic gates Message-ID: An HTML attachment was scrubbed... URL: From edmyers at stanford.edu Wed Aug 22 10:32:42 2007 From: edmyers at stanford.edu (Ed Myers) Date: Wed, 22 Aug 2007 10:32:42 -0700 Subject: Fwd: Re: Special Request for very limited presence of BISMUTH Message-ID: <6.2.5.6.2.20070822102345.03c1d000@stanford.edu> All, I've had a couple of discussion with Betty regarding this request. I would like to get your feedback on how best to approach this problem. There are open patches of Bi deposited on the backside of the wafer. Betty wants to do a through wafer etch stopping on nitride. The Bi will not be exposed to the plasma, but will be exposed to the backside cooling gas. From a contact contamination point of view, they will be suppling their own carrier chuck. The concern I have is Bismuths is below our vapor pressure cut-off. Using this standard, we would not readily let the samples in our gold contaminated equipment set. What are your opinions? Would a layer of photoresist be sufficient to protect the Bi from sublimation? Ed >X-Sieve: CMU Sieve 2.3 >Delivered-To: edmyers at stanford.edu >Date: Fri, 17 Aug 2007 09:13:43 -0700 >From: Betty Young >To: Ed Myers >Subject: Re: Special Request for very limited presence of BISMUTH >User-Agent: Internet Messaging Program (IMP) H3 (4.1.4) >Authenticated-User: bayoung >X-Originating-IP: 67.169.52.3 > >Hi Ed, > >As it stands now, our wafer has 100 micron patches of Bi deposited as >a final step. It is exposed. (Please see the attached jpg showing our >3" wafer with locations of patches.) > >However, we have made an o-ring based vacuum chuck adapter piece for >the dry etcher that holds the wafer with the Bi side "hidden" except >for a small pump-out port. So the Bi would have very little exposure >(except when mounting the wafer). > > >Thanks for considering this. We really do appreciate it. >I'd be happy to meet with you to discuss details, if that would help >in the decision-making process (either way). >Betty > >Quoting Ed Myers : > >>Betty, >> >>I ran out of coffee before I finished on Wednesday. >> >>I need a better understanding of you sample configuration. Will Bi be >>exposed, or will it be buried? Bi is below our vapor pressure cut-of >>for material we allow in our vacuum systems. It will be real helpful to >>get a better understanding of your structure, since we have to >>compromise our rules. >> >>Thanks, >>Ed >> >>At 12:32 PM 7/20/2007, you wrote: >> >>>Dear All, >>> >>>Astrid Tomada and I have a few wafers that we need to expose and then >>>dry-etch (to define SiN membranes on a Si substrate). These wafers >>>have timy patches of Bi on the side we will not etch. We have NEVER >>>brought Bi into the lab. We now are in the need to do so, if at all >>>possible. >>> >>>Requests: >>>(1) To use our own, dedicated, 3" wafer holder to dry-etch through a >>>patterned Si wafer. The Bi patches would be on the side of the wafer >>>almost entirely coverd by one small cooling-gas hole on the "backside" >>>of the 3" adapter plate. >>> >>>(2) We would also need to do the photolith step ("backside") preceding >>>the dry-etch to define the windows for the membranes. We could coat >>>the "Bi" side with PR for protection in many of these steps. >>> >>>Thank you very much for your consideration. >>>I would appreciate the opportunity to speak with any of you about the >>>details of this request, if that would be helpful. >>> >>>As always, we will ONLY bring the Bi-processed wafers in the lab if we >>>receive authorization. Needless to say, we are very eager to meet any >>>constraints you may have if it will allow us to do the dry-etch in >>>CIS! (We have found no other options for this step.) >>> >>>Thanks very much, >>>Betty Young > From mkoto at stanford.edu Wed Aug 22 16:08:04 2007 From: mkoto at stanford.edu (mkoto at stanford.edu) Date: Wed, 22 Aug 2007 16:08:04 -0700 Subject: APTES Message-ID: <20070822160804.c2zza3lo8wisscc0@webmail.stanford.edu> Hello, I intend to use APTES(3-AMINOPROPYLTRIETHOXYSILANE) inside Lab, WBSOLVENT. Attached is MSDS of this chemical. This is very basic silane coupling chemical. Please let me know if there are any concern for it and I can use it or not. Best regards, Makoto *************************************************** Makoto Koto Visiting Scholar 476 Lomita Mall 244 McCullough Building Stanford, CA 94305-4045 *************************************************** -------------- next part -------------- A non-text attachment was scrubbed... Name: xMSDS-3_Aminopropyltriethoxysilane-16780.pdf Type: application/pdf Size: 77686 bytes Desc: not available URL: From mtang at stanford.edu Wed Aug 22 17:23:29 2007 From: mtang at stanford.edu (Mary Tang) Date: Wed, 22 Aug 2007 17:23:29 -0700 Subject: APTES In-Reply-To: <20070822160804.c2zza3lo8wisscc0@webmail.stanford.edu> References: <20070822160804.c2zza3lo8wisscc0@webmail.stanford.edu> Message-ID: <46CCD381.6080704@stanford.edu> Hi Makoto -- This is already an approved chemical for wbsolvent. If you store it in the lab, it should be kept in the small Flammables cabinet, in the personal chemicals bin. Please see Mahnaz or Ed about getting a yellow label for your chemical. The standard procedures for using this chemical are dilution in solvent at wbsolvent and soaking or dipping your sample at room temperature. If there are changes to this procedure (such as heating the solution) let us know. The only safety concern is the solvent that you will be using for diluting this chemical. If it is one of the standard chemicals (isopropanol, ethanol, or methanol) and you are using dilute solutions (less than 5% APTES) then it is OK to dispose of the waste in the solvent carboy. If you are using any other non-standard solvents (such as toluene), please let us know so we can discuss disposal of waste. The other possible concern is contamination, since any glassware or labware you use will become coated with this material. Please use your own glassware and labware. If you need any protocols or procedures for use of this material, let us know as we have some materials. Mary mkoto at stanford.edu wrote: > Hello, > > I intend to use APTES(3-AMINOPROPYLTRIETHOXYSILANE) inside Lab, > WBSOLVENT. > Attached is MSDS of this chemical. This is very basic silane coupling > chemical. > > Please let me know if there are any concern for it and I can use it or > not. > > Best regards, > > Makoto > > *************************************************** > Makoto Koto Visiting Scholar > 476 Lomita Mall 244 McCullough Building > Stanford, CA 94305-4045 > *************************************************** -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From newsletter at nilt.com Thu Aug 23 23:20:39 2007 From: newsletter at nilt.com (newsletter at nilt.com) Date: Fri, 24 Aug 2007 08:20:39 +0200 Subject: NILT nanonews august 24: Nanotubes turn paper into a power source, understanding nanotechnology, STT-RAM Message-ID: An HTML attachment was scrubbed... URL: From rkuse at pacificbiosciences.com Mon Aug 27 15:44:12 2007 From: rkuse at pacificbiosciences.com (Ron Kuse) Date: Mon, 27 Aug 2007 15:44:12 -0700 Subject: PECVD Process Change Request Message-ID: I would like to change the temperature of PECVD STS tool from 350 deg. C to 300, 250, and 200 to investigate effect on pinhole formation when deposited on 100nm Al film. At 350 deg. C, a large number of pinholes form. Images are available upon request but will not be emailed as they include proprietary design information. Thank you. -------------- next part -------------- An HTML attachment was scrubbed... URL: From mcvittie at cis.Stanford.EDU Mon Aug 27 16:18:34 2007 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Mon, 27 Aug 2007 16:18:34 -0700 (PDT) Subject: PECVD Process Change Request In-Reply-To: Message-ID: Ron, We have seen this problem before with Al. Your approach is in the right direction. Years ago, we developed a 300 C LTO process for this same reason. In the LTO case we were limited to a min temp of 300C. We deposited about 500A at 300C before finishing the deposition at 400C. This gave a big improvement over a complete deposition at 400C. For the PECVD system, the temp is kept at 350C to delay flaking from the chamber walls so we can do more runs before cleaning the system. At this time, I am not sure we have any of the data from the test runs used to determine that it was best to leave the system at 350C. We will need to talk to Jeanie and see what data before we can answer your request. Jim On Mon, 27 Aug 2007, Ron Kuse wrote: > I would like to change the temperature of PECVD STS tool from 350 deg. C > to 300, 250, and 200 to investigate effect on pinhole formation when > deposited on 100nm Al film. At 350 deg. C, a large number of pinholes > form. Images are available upon request but will not be emailed as they > include proprietary design information. Thank you. > > -- -------------------------------------------------------------- Jim McVittie, Ph.D. Senior Research Scientist Allen Center for Integrated Systems Electrical Engineering Stanford University jmcvittie at stanford.edu Rm. 336, 330 Serra Mall Fax: (650) 723-4659 Stanford, CA 94305-4075 Tel: (650) 725-3640 From rkuse at pacificbiosciences.com Mon Aug 27 17:21:40 2007 From: rkuse at pacificbiosciences.com (Ron Kuse) Date: Mon, 27 Aug 2007 17:21:40 -0700 Subject: PECVD Process Change Request In-Reply-To: References: Message-ID: Jim, Thanks for your comments. I'll wait to hear from Jeannie if she is okay with the lower temperature. Naturally, I'll do any necessary cleaning after my experiments. Thanks, Ron -----Original Message----- From: Jim McVittie [mailto:mcvittie at cis.Stanford.EDU] Sent: Monday, August 27, 2007 4:19 PM To: Ron Kuse Cc: specmat at snf.stanford.edu Subject: Re: PECVD Process Change Request Ron, We have seen this problem before with Al. Your approach is in the right direction. Years ago, we developed a 300 C LTO process for this same reason. In the LTO case we were limited to a min temp of 300C. We deposited about 500A at 300C before finishing the deposition at 400C. This gave a big improvement over a complete deposition at 400C. For the PECVD system, the temp is kept at 350C to delay flaking from the chamber walls so we can do more runs before cleaning the system. At this time, I am not sure we have any of the data from the test runs used to determine that it was best to leave the system at 350C. We will need to talk to Jeanie and see what data before we can answer your request. Jim On Mon, 27 Aug 2007, Ron Kuse wrote: > I would like to change the temperature of PECVD STS tool from 350 deg. C > to 300, 250, and 200 to investigate effect on pinhole formation when > deposited on 100nm Al film. At 350 deg. C, a large number of pinholes > form. Images are available upon request but will not be emailed as they > include proprietary design information. Thank you. > > -- -------------------------------------------------------------- Jim McVittie, Ph.D. Senior Research Scientist Allen Center for Integrated Systems Electrical Engineering Stanford University jmcvittie at stanford.edu Rm. 336, 330 Serra Mall Fax: (650) 723-4659 Stanford, CA 94305-4075 Tel: (650) 725-3640 From newsletter at nilt.com Thu Aug 30 23:42:39 2007 From: newsletter at nilt.com (newsletter at nilt.com) Date: Fri, 31 Aug 2007 08:42:39 +0200 Subject: NILT nanonews august 31: Photon-transistors, nanogels for controlled drug delivery, nanosensor predicts asthma attacks Message-ID: <880159ef845f3926272ecdf10013caa6@nilt.com> An HTML attachment was scrubbed... URL: