Proposal for non-standard process in stsetch

Nahid Harjee nharjee at stanford.edu
Wed Aug 15 21:08:51 PDT 2007


SpecMat Committee,

I am working with SOI wafers to build piezoresistive cantilevers. The
interconnect on the cantilevers is a Cr/Au stack. To release the
cantilevers, I am seeking permission to use stsetch to etch through the
handle layer to the buried oxide, provided that the Cr/Au is fully
encapsulated and is never exposed to the plasma. Below is the material stack
I propose:

Plasma (SF6/C4F8)

Resist (7 um, patterned)
Si (530 um handle layer)
SiO2 (1 um buried oxide)
Si (6 um device layer, patterned into cantilevers)
SiO2 (100 nm)
Cr (10 nm)
Au (100 nm)
Resist (15 um, unpatterned)
Aluminum holder

He cooling

I believe that this process has been approved by SpecMat in the past. Please
let me know if you have any questions/comments or would like more details
about my process. I look forward to your response.

Thanks,

nh

-- 
Nahid Harjee
Ph.D. Candidate
Electrical Engineering
Stanford University
408-761-8651
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