Proposal for non-standard process in stsetch

Jim McVittie mcvittie at cis.Stanford.EDU
Wed Aug 15 22:53:47 PDT 2007


A few years back, a number of experiments were done to see if we could 
bury Au so that a Au contaminated wafer could be etched in the STS without 
exposing the plasma or the chuck to Au. At that time, all the attempts 
failed. We always detected Au on the surface.  Part of the problem is that 
resist always picks up Au from the etch solution and then deposits it back 
on the wafer when the resist is stripped.


On Wed, 15 Aug 2007, Nahid Harjee wrote:

> SpecMat Committee,
> I am working with SOI wafers to build piezoresistive cantilevers. The
> interconnect on the cantilevers is a Cr/Au stack. To release the
> cantilevers, I am seeking permission to use stsetch to etch through the
> handle layer to the buried oxide, provided that the Cr/Au is fully
> encapsulated and is never exposed to the plasma. Below is the material stack
> I propose:
> Plasma (SF6/C4F8)
> Resist (7 um, patterned)
> Si (530 um handle layer)
> SiO2 (1 um buried oxide)
> Si (6 um device layer, patterned into cantilevers)
> SiO2 (100 nm)
> Cr (10 nm)
> Au (100 nm)
> Resist (15 um, unpatterned)
> Aluminum holder
> He cooling
> I believe that this process has been approved by SpecMat in the past. Please
> let me know if you have any questions/comments or would like more details
> about my process. I look forward to your response.
> Thanks,
> nh

Jim McVittie, Ph.D.    			Senior Research Scientist 
Allen Center for Integrated Systems     Electrical Engineering
Stanford University             	jmcvittie at
Rm. 336, 330 Serra Mall			Fax: (650) 723-4659
Stanford, CA 94305-4075			Tel: (650) 725-3640

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