Proposal for non-standard process in stsetch

Mary Tang mtang at
Thu Aug 16 08:26:07 PDT 2007

Hi Jim, et al --

Yes, I remember you mentioning these experiments...  (By the way, would 
you still happen to have this data and be willing to share it?  It seems 
to me that there was an awful lot of really useful information in it 
about etching, furnaces, and cleans.)

Regarding Nahid's request....  as I vaguely recall from the last time 
this came up (pre-Beth Pruitt) the policy was to allow gold in the 
stsetch provided:

1.  If the gold was patterned that it had been done by lift-off rather 
than etching
2.  No gold exposed to plasma -- that it was completely covered with resist.

The rationale was that gold is pretty inert in its noble metal state, 
but that contamination becomes an issue once wet etching is done and 
gold appears in various oxidation states which are soluble (and appear 
all over the wafer).  It was agreed not to support Beth's request for Au 
in stsetch when she was a grad student because the above two conditions 
were not met, so she went to UCSB.  I seem to recall (perhaps 
incorrectly) that the TXRF experiments were done on wafers in which the 
gold had been patterned using KI etchant, which would leave soluble gold 
atoms on the wafer surfaces to examine the worst case scenario of gold 
in stsetch....  Nahid is proposing to cover unpatterned gold present on 
the backside of the wafers with resist -- and to use the holder.  It 
would seem that the cross-contamination risk should be low....

My two cents'


Jim McVittie wrote:
> Hi,
> A few years back, a number of experiments were done to see if we could 
> bury Au so that a Au contaminated wafer could be etched in the STS without 
> exposing the plasma or the chuck to Au. At that time, all the attempts 
> failed. We always detected Au on the surface.  Part of the problem is that 
> resist always picks up Au from the etch solution and then deposits it back 
> on the wafer when the resist is stripped.
> 	Jim     
> On Wed, 15 Aug 2007, Nahid Harjee wrote:
>> SpecMat Committee,
>> I am working with SOI wafers to build piezoresistive cantilevers. The
>> interconnect on the cantilevers is a Cr/Au stack. To release the
>> cantilevers, I am seeking permission to use stsetch to etch through the
>> handle layer to the buried oxide, provided that the Cr/Au is fully
>> encapsulated and is never exposed to the plasma. Below is the material stack
>> I propose:
>> Plasma (SF6/C4F8)
>> Resist (7 um, patterned)
>> Si (530 um handle layer)
>> SiO2 (1 um buried oxide)
>> Si (6 um device layer, patterned into cantilevers)
>> SiO2 (100 nm)
>> Cr (10 nm)
>> Au (100 nm)
>> Resist (15 um, unpatterned)
>> Aluminum holder
>> He cooling
>> I believe that this process has been approved by SpecMat in the past. Please
>> let me know if you have any questions/comments or would like more details
>> about my process. I look forward to your response.
>> Thanks,
>> nh

Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
mtang at

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