Fwd: Re: Special Request for very limited presence of BISMUTH
edmyers at stanford.edu
Wed Aug 22 10:32:42 PDT 2007
I've had a couple of discussion with Betty regarding this request. I
would like to get your feedback on how best to approach this problem.
There are open patches of Bi deposited on the backside of the
wafer. Betty wants to do a through wafer etch stopping on
nitride. The Bi will not be exposed to the plasma, but will be
exposed to the backside cooling gas. From a contact contamination
point of view, they will be suppling their own carrier chuck. The
concern I have is Bismuths is below our vapor pressure
cut-off. Using this standard, we would not readily let the samples
in our gold contaminated equipment set.
What are your opinions? Would a layer of photoresist be sufficient
to protect the Bi from sublimation?
>X-Sieve: CMU Sieve 2.3
>Delivered-To: edmyers at stanford.edu
>Date: Fri, 17 Aug 2007 09:13:43 -0700
>From: Betty Young <bayoung at stanford.edu>
>To: Ed Myers <edmyers at stanford.edu>
>Subject: Re: Special Request for very limited presence of BISMUTH
>User-Agent: Internet Messaging Program (IMP) H3 (4.1.4)
>As it stands now, our wafer has 100 micron patches of Bi deposited as
>a final step. It is exposed. (Please see the attached jpg showing our
>3" wafer with locations of patches.)
>However, we have made an o-ring based vacuum chuck adapter piece for
>the dry etcher that holds the wafer with the Bi side "hidden" except
>for a small pump-out port. So the Bi would have very little exposure
>(except when mounting the wafer).
>Thanks for considering this. We really do appreciate it.
>I'd be happy to meet with you to discuss details, if that would help
>in the decision-making process (either way).
>Quoting Ed Myers <edmyers at stanford.edu>:
>>I ran out of coffee before I finished on Wednesday.
>>I need a better understanding of you sample configuration. Will Bi be
>>exposed, or will it be buried? Bi is below our vapor pressure cut-of
>>for material we allow in our vacuum systems. It will be real helpful to
>>get a better understanding of your structure, since we have to
>>compromise our rules.
>>At 12:32 PM 7/20/2007, you wrote:
>>>Astrid Tomada and I have a few wafers that we need to expose and then
>>>dry-etch (to define SiN membranes on a Si substrate). These wafers
>>>have timy patches of Bi on the side we will not etch. We have NEVER
>>>brought Bi into the lab. We now are in the need to do so, if at all
>>>(1) To use our own, dedicated, 3" wafer holder to dry-etch through a
>>>patterned Si wafer. The Bi patches would be on the side of the wafer
>>>almost entirely coverd by one small cooling-gas hole on the "backside"
>>>of the 3" adapter plate.
>>>(2) We would also need to do the photolith step ("backside") preceding
>>>the dry-etch to define the windows for the membranes. We could coat
>>>the "Bi" side with PR for protection in many of these steps.
>>>Thank you very much for your consideration.
>>>I would appreciate the opportunity to speak with any of you about the
>>>details of this request, if that would be helpful.
>>>As always, we will ONLY bring the Bi-processed wafers in the lab if we
>>>receive authorization. Needless to say, we are very eager to meet any
>>>constraints you may have if it will allow us to do the dry-etch in
>>>CIS! (We have found no other options for this step.)
>>>Thanks very much,
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