rostam at stanford.edu
Fri Mar 21 17:50:47 PDT 2008
I was wondering if I can somehow do the following process at SNF:
I have a clean Si wafer. I pattern Ir (25nm thick) on the wafer
through liftoff. Then I coat it with some insulator like any of
LP-CVD/PE-CVD Oxide/Nitride (doesn't matter which). Then I want to
pattern the wafer and etch the insulating layer and then the Si 30um
deep in STS or STS2. Only the areas with no Ir on them will be etched;
i.e. Ir is not an etch mask.
I don't have any requirements on using a specific insulating material
or machine (for depositing Ir, for depositing insulating layer, for
etching insulating layer) except for etching the silicon which should
be done by STS or STS2. The reason for wanting to use STS/STS2 is
because my structure has trenches 10um wide and 30um deep and two
neighboring trenches are 1um apart and I'm not aware of any other
machine that can do that.
I was wondering if there is any sequence of procedures/machines that
would allow me to this process.
In case I can't do this, is it possible to do the above with Pt instead of Ir?
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