[Fwd: Parylene]

Nancy Latta nlatta at stanford.edu
Fri May 9 11:08:46 PDT 2008


As I am reading this, what is being requested in EtchWorld is to do deep 
Si RIE in an STS on wafers with no processing other than litho.  Fine 
with me.  Then later a parylene etch using a contamined etcher (resist 
as an etch mask?  If yes, selectivity to parylene?).  Again, fine with 
me in drytek1 or 4, mrc or pquest- they all have O2 and Fl if needed.

Hope this helps,


Mahnaz Mansourpour wrote:

> Hello all,
> I already have talked to him , I need to look at the msds and decide 
> on the yes oven part of it, the rest of litho is ok.  What do every 
> one think of the etching part of it?
> mahnaz
> -------- Original Message --------
> Subject: 	Parylene
> Date: 	Thu, 8 May 2008 16:01:26 -0700
> From: 	"Vikram Mukundan" <mvikram at stanford.edu>
> Organization: 	Stanford University
> To: 	"Mahnaz Mansourpour" <mahnaz at snf.stanford.edu>
> Hi Mahnaz,
> I had talked to you this afternoon about allowing parylene coated 
> wafers in the litho and possibly in the plasma. I have attached some 
> files related to this for your reference.
> 1. My process run with highlighted steps after parylene-N deposition.
> 2. MSDS for parylene-N.
> 3. A paper on the thermal stability of parylene-N (they are stable up 
> to 350 C)
> 4. A paper on plasma etching techniques on parylene coatings using O2 
> plasma, RIE and Bosch process. This paper involves lithography with 
> HMDS prime, spin resist, baking and developing. In a private 
> communication, the author of this paper has mentioned that parylene is 
> inert in most processes.
> My minimum requirement would be to be able to perform litho steps on 
> coated wafers. If things work out well I would like to see if I can 
> use one of the plasma etchers. My process is gold contaminated at this 
> stage.
> Please let me know if you need any more information.
> thank you for the help,
> Vikram

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