From james.kim at sundiode.com Thu Oct 1 16:32:58 2009 From: james.kim at sundiode.com (James Kim) Date: Thu, 1 Oct 2009 16:32:58 -0700 Subject: SpecMat's Consideration for Spin-On-Glass Material Message-ID: <003101ca42ef$830f5ec0$892e1c40$@kim@sundiode.com> Hello, I submit this request for specmat committee's approval. Please let me know if anything else is needed. Thank you. Coral Login: jameskim Phone no.:408-234-6562 Email: jameskim at snf.stanford.edu or james.kim at sundiode.com Company: Sundiode, Inc. Material: Accuglass T-12B (512B) Spin-On-Glass (MSDS attached) Manufacturer: Honeywell Electronic Materials 3500 Garret Drive, Santa Clara, CA 95054 Reason for Request: I am developing a procedure to utilize the substance as a planarizing agent on compound-semiconductor devices we are building. I will use it to coat a wafer (2 inch) under various conditions. Later on, I will also develop a procedure to etch down on the glass material in controlled manner to reveal certain features on the wafer. Process flow: Initially, I will simply use the headway spin coater to coat various wafers under various conditions, cure, and then examine the wafers using SEM. Later on, controlled etching to etch a specific amount of material to reveal parts of the semiconductor on the wafer will be developed, requiring the use of wet bench (contaminated) for wet etching. The etched structures will be examined using SEM. Subsequently, metal deposition (Al) is planned on the spin-coated, cured, etched wafer sample. Amount: I would like to bring 2 bottles, each with 125mL. Storage: They need to be refrigerated at 0-4C. The bottles are clearly labeled with original manufacturer's lables. Disposal of excess: The bulk of the material is solvent: ethanol, isopropyl alcohol and smaller amount of acetone. Non-solvent material is Methyl siloxane polymer. Excess (during spin coating for example) will be treated as flammable and disposed of in the same way photoresist is disposed of. All of the material will be used in the next 6 months. James C. Kim, Ph.D. CEO, Sundiode, Inc. 1398 Borregas Ave., Sunnyvale, CA 94089 Electronic james.kim at sundiode.com Company +1.408.400.9182 Mobile +1.408.234.6562 Fax +1.408.624.9332 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Honeywell Accuglass T-12B (512B) Spin-On Glass.pdf Type: application/pdf Size: 130042 bytes Desc: not available URL: From mtang at stanford.edu Fri Oct 2 10:21:34 2009 From: mtang at stanford.edu (Mary Tang) Date: Fri, 02 Oct 2009 10:21:34 -0700 Subject: SpecMat's Consideration for Spin-On-Glass Material In-Reply-To: <003101ca42ef$830f5ec0$892e1c40$@kim@sundiode.com> References: <003101ca42ef$830f5ec0$892e1c40$@kim@sundiode.com> Message-ID: <4AC6369E.5020705@stanford.edu> Hi James -- Please give us some more details on your process flow. Where and how do you plan to cure your films? And then eventually which Al deposition system do you think you'd like to use? Thanks, Mary James Kim wrote: > > Hello, I submit this request for specmat committee?s approval. Please > let me know if anything else is needed. Thank you. > > Coral Login: jameskim > > Phone no.:408-234-6562 > > Email: jameskim at snf.stanford.edu or > james.kim at sundiode.com > > Company: Sundiode, Inc. > > Material: Accuglass T-12B (512B) Spin-On-Glass (MSDS attached) > > Manufacturer: Honeywell Electronic Materials 3500 Garret Drive, Santa > Clara, CA 95054 > > Reason for Request: I am developing a procedure to utilize the > substance as a planarizing agent on compound-semiconductor devices we > are building. I will use it to coat a wafer (2 inch) under various > conditions. Later on, I will also develop a procedure to etch down on > the glass material in controlled manner to reveal certain features on > the wafer. > > Process flow: Initially, I will simply use the headway spin coater to > coat various wafers under various conditions, cure, and then examine > the wafers using SEM. Later on, controlled etching to etch a specific > amount of material to reveal parts of the semiconductor on the wafer > will be developed, requiring the use of wet bench (contaminated) for > wet etching. The etched structures will be examined using SEM. > Subsequently, metal deposition (Al) is planned on the spin-coated, > cured, etched wafer sample. > > Amount: I would like to bring 2 bottles, each with 125mL. > > Storage: They need to be refrigerated at 0-4C. The bottles are clearly > labeled with original manufacturer?s lables. > > Disposal of excess: The bulk of the material is solvent: ethanol, > isopropyl alcohol and smaller amount of acetone. Non-solvent material is > > Methyl siloxane polymer. Excess (during spin coating for example) will > be treated as flammable and disposed of in the same way photoresist is > disposed of. All of the material will be used in the next 6 months. > > James C. Kim, Ph.D. > > CEO, Sundiode, Inc. > > 1398 Borregas Ave., Sunnyvale, CA 94089 > > Electronic james.kim at sundiode.com > > Company +1.408.400.9182 Mobile +1.408.234.6562 Fax +1.408.624.9332 > From mtang at stanford.edu Wed Oct 7 12:30:58 2009 From: mtang at stanford.edu (Mary Tang) Date: Wed, 07 Oct 2009 12:30:58 -0700 Subject: Potassium dichromate, CAS# 7778-50-9 In-Reply-To: <18BDA344D5E5A246B9BE928D8459D355014FDD9F@ngm05.nanogram.com> References: <18BDA344D5E5A246B9BE928D8459D355014FDD9F@ngm05.nanogram.com> Message-ID: <4ACCEC72.3010008@stanford.edu> Hi Khanh -- As discussed, this should be fine. However, please collect waste locally and label appropriately instead of using the HF drain. Thanks, Mary Khanh Hoang wrote: > > > > Hello Mahnaz and Marry, > > > > I would like to bring a new chemical into the SNF lab. Here is the > information: > > > > (1) Contact Information: > > ? Name: Khanh Hoang > > ? Coral login: khoang > > NanoGram Corp. > > 165 Topaz Street > > Milpitas, CA 95035 > > Tel: (408) 719-5356 > > Fax: (408) 262-6290 > > Cell phone: (408) 786-6441 > > > > (2) The chemical: Potassium dichromate; > > * Synonyms: Potassium bichromate > > * CAS#: 7778-50-9 > > * Storage group: *E* - Compatible Oxidizers, Organic Peroxides, > and Acids. > > * Main hazard class: Oxidizers > > > > (3) Vendor/ Manufacturer info: > > ? Vendor: Sigma-Aldrich, > http://www.sigmaaldrich.com/catalog/ProductDetail.do?lang=en&N4=483044|ALDRICH&N5=SEARCH_CONCAT_PNO|BRAND_KEY&F=SPEC > > > ? Phone: 800-325-3010 > > (4) Reason for request: > > ? We will perform Secco etching on polycrystalline Si wafers > to etch defects. > > ? Secco etch recipe: Mixture of *HF (48%)* + *K_2 Cr_2 O_7 * > (*44 g K_2 Cr_2 O_7 * dissolved in *1 l* of the of *H_2 O, or 0.15 M) > in a ratio of 2:1* > > > > (5) Process flow: > > * We will first dissolve Potassium dichromate with deionized water > in a HDPE (high density polyethylene) plastic bottle at the > chemicals handling bench (outside of the cleanroom). > * The solution will then be transferred by a staff member to the > Pass-through Carts. > * We will mix the solution with HF (48%) and perform the etching > process at the wbgen-hpr and use the Gold-contaminated labwares. > * After the etching process we will process the samples outside of > the cleanroom. However the purity level of the purchased > potassium dichromate is greater than 99.99% trace metals basis. > > > > (6) Amount and form: > > ? Amount: 44 grams > > ? Form: solid > > ? I will dissolve 44 grams in 1L of deionized water. > > > > (7) Storage: the potassium dichromate solution will be stored on > top of one of the Pass-through Carts or in the bulk storage area. > > > > (8) Disposal: the spent mixture of potassium dichromate solution > and HF will be disposed in the HF drain. Excess or unused potassium > dichromate solution will be collected locally according to the SNF > regulation (disposed in a clean, empty waste container, attached to > the bottle with a filled hazardous waste disposal label, and place the > container on the hazardous waste shelf in the chemcial pass-through). > > > > Please let me know if I can perform this task at SNF. > > > > Thanks so much for your help, > > > > Khanh Hoang > > > > This message is for the designated recipient only and may contain > privileged, proprietary, or otherwise private information. > Unauthorized use or disclosure of this e-mail is strictly prohibited. > If you have received it in error, please notify the sender immediately > and delete the original. > > > From nharjee at stanford.edu Thu Oct 8 21:08:53 2009 From: nharjee at stanford.edu (Nahid Harjee) Date: Thu, 8 Oct 2009 21:08:53 -0700 Subject: Request to use lampoly or p5000 to etch semi-clean wafers Message-ID: <2feeb6700910082108gfec52f5xec57f35c3afb0afd@mail.gmail.com> SpecMat, I am designing a process to fabricate single crystal silicon cantilevers that are 3 um thick. The narrowest cantilevers are 14 um wide and have 4 "legs" at the clamped end that are 2 um wide. I am trying to select a tool to etch the 3 um of silicon to define the cantilever that will produce straight sidewalls. In the past, I have used stsetch to define wider cantilevers. However, I am concerned that the scalloping resulting from this tool will make it difficult to etch the 2 um legs of the new design. Thus, I am writing to propose that I perform this etch with HBr/Cl2 chemistry in lampoly or p5000. What makes this process non-standard is that my wafers will be semi-clean at this point. The step prior to defining the cantilevers is deposition of 1500 A of Al in gryphon which is then patterned with a wet etch in Al-11. During the Si etch, the Al will never be exposed to the plasma (it will be covered by 3 um of resist). However, there is a chance that there will be trace Al on the exposed Si from the Al-11 bath. At the most recent process clinic, Keith Best raised the point that there may be exposed Al in the EBR region of my wafers. In order to minimize this possibility, I can use 5 mm EBR for the Al litho and 2 mm EBR for the cantilever litho, ensuring there's a buffer of 3 mm of resist with no Al below it. I look foward to hearing your decision on the proposed process or if there is a tool that is better suited for this process, I welcome any suggestions. Thanks, nh -- Nahid Harjee Ph.D. Candidate Electrical Engineering Stanford University 408-761-8651 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Fri Oct 9 08:46:33 2009 From: mtang at stanford.edu (Mary Tang) Date: Fri, 09 Oct 2009 08:46:33 -0700 Subject: Request to use lampoly or p5000 to etch semi-clean wafers In-Reply-To: <2feeb6700910082108gfec52f5xec57f35c3afb0afd@mail.gmail.com> References: <2feeb6700910082108gfec52f5xec57f35c3afb0afd@mail.gmail.com> Message-ID: <4ACF5AD9.2070204@stanford.edu> Hi all -- We really need to get back to this question of how we are going to accommodate requests for metal-containing materials in clean dry etch tools. This request strikes me as being an incremental step in that direction.... As for as lampoly is concerned (and I suspect would also apply to P5000etch), this seems reasonable. The EBR margin should be sufficient (a wafer without EBR risks sticking to the lampoly clamp ring.) And the clamp is made from alumina, so I don't think there's an appreciable contamination risk from whatever trace Al may remain on exposed wafer surfaces. I vote that we OK this request -- with the proviso that we update the documentation to describe in detail the rationale and conditions under which semi-clean wafers can be processed in lampoly (and p5000etch.) So... do we have a quorum? Mary Nahid Harjee wrote: > SpecMat, > > I am designing a process to fabricate single crystal silicon > cantilevers that are 3 um thick. The narrowest cantilevers are 14 um > wide and have 4 "legs" at the clamped end that are 2 um wide. I am > trying to select a tool to etch the 3 um of silicon to define the > cantilever that will produce straight sidewalls. In the past, I have > used stsetch to define wider cantilevers. However, I am concerned that > the scalloping resulting from this tool will make it difficult to etch > the 2 um legs of the new design. Thus, I am writing to propose that I > perform this etch with HBr/Cl2 chemistry in lampoly or p5000. What > makes this process non-standard is that my wafers will be semi-clean > at this point. The step prior to defining the cantilevers is > deposition of 1500 A of Al in gryphon which is then patterned with a > wet etch in Al-11. During the Si etch, the Al will never be exposed to > the plasma (it will be covered by 3 um of resist). However, there is a > chance that there will be trace Al on the exposed Si from the Al-11 > bath. At the most recent process clinic, Keith Best raised the point > that there may be exposed Al in the EBR region of my wafers. In order > to minimize this possibility, I can use 5 mm EBR for the Al litho and > 2 mm EBR for the cantilever litho, ensuring there's a buffer of 3 mm > of resist with no Al below it. > > I look foward to hearing your decision on the proposed process or if > there is a tool that is better suited for this process, I welcome any > suggestions. > > Thanks, > > nh > > -- > Nahid Harjee > Ph.D. Candidate > Electrical Engineering > Stanford University > 408-761-8651 -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Fri Oct 9 09:20:44 2009 From: mtang at stanford.edu (Mary Tang) Date: Fri, 09 Oct 2009 09:20:44 -0700 Subject: SiO2 deposition in innotec ebeam evaporator In-Reply-To: <521462444.6894251252455785038.JavaMail.root@zm08.stanford.edu> References: <521462444.6894251252455785038.JavaMail.root@zm08.stanford.edu> Message-ID: <4ACF62DC.3040003@stanford.edu> Hi all - Did we ever get back to this person? Mary Min-Kyo Seo wrote: > Dear Spec Mat panel, > > I am a postdoc in the group of Mark Brongersma in the MSE department. > > I would like to ask about innotec ebeam evaporator. > Can I perform SiO2 deposition? > > All the best, > Min-Kyo Seo > ----------------------------------------------------------------------------- > Postdoctoral Scholar > Mark Brongersma's Group > Department of Materials Science and Engineering > McCollough Building #216 > Stanford University > Cell: (650)353-0614 Fax: (650)724-9851 > E-mail: mkseo at stanford.edu; minkyo.seo at gmail.com > > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Fri Oct 9 09:21:14 2009 From: mtang at stanford.edu (Mary Tang) Date: Fri, 09 Oct 2009 09:21:14 -0700 Subject: TXRF results for continued processing on semi-clean tools... In-Reply-To: <3F24868DDBDC7B46B2289E33B58C4CB11F5DDE5118@QUSWAMI-DSRV1.quswami.local> References: <3F24868DDBDC7B46B2289E33B58C4CB11F5DDE5118@QUSWAMI-DSRV1.quswami.local> Message-ID: <4ACF62FA.6080200@stanford.edu> And Robert? Mary Robert Huang wrote: > > Dear SNF Specmat Committee Members: > > > > I would like to ask for the committee?s approval to run 4? silicon > wafers on SNF semi-clean tools (mainly the AG4100 RTA machine) that > have been deposited with titanium oxide via e-beam evaporation through > an external vendor. We have worked with this vendor to reduce metal > contamination levels below the 1e12/cm2 ?semi-clean? specification > limit. As you will see in the attached file, prior to taking > corrective action, there were locations on a test wafer that clearly > exhibited Fe and Cu levels above the 1e12/cm2 limit. However, after > detailed investigation, several steps were taken to clean up the tool > with the positive results shown in the attached file from the last > test wafer. Note that the TXRF results were provided by Evans > Analytical Group (EAG) using a W source which can detect elements from > S-Zn and Mo-Hf. If an element is not listed in the table, it was not > detected in the analysis. Evans has a detailed procedure for > calibration of their TXRF equipment and guarantee reproducibility to > within the reported results (uncertainty values in the table are > 1sigma standard deviations) through use of calibrated Vanadium and > Nickel references. Also note that due to overlap in emission > energies, EAG can only report upper bounds for some of the elements > (specifically the Cu and Hf energy peaks overlap) and the background > matrix Ti energy peak interferes with the Cl, K, and Ca peaks. > > > > If there are any questions, please do not hesitate to contact me. > > > > Sincerely, > > > > Robert Huang > > Director, Process and Device Technology > > QuSwami, Inc. > > 505 Montgomery St., Suite 300 > > San Francisco, CA 94111 > > 415-834-9910 (Office) > > 408-854-0450 (Cell) > > roberth at quswami.com > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mcvittie at cis.Stanford.EDU Fri Oct 9 10:07:05 2009 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Fri, 9 Oct 2009 10:07:05 -0700 (PDT) Subject: Request to use lampoly or p5000 to etch semi-clean wafers In-Reply-To: <4ACF5AD9.2070204@stanford.edu> Message-ID: Mary, Back at the beginning of time, we wanted to keep all metals of the Lam and push requests like this to the P5000. The idea was to reserve the Lam for frontend processes where being metal free is most important. However, yrs back when we did TXRF measurements on the Lam, we found that it was no better then the P5000 Si chamber and the key was the post etch cleaning. So I do not think it make much difference from a metal contamination viewpoint whether this work is done in the Lam or P5000. Since this is not a high resolution etch, I would recommand he use the P-5000. By the way, the Lam intrically has Al comtamination because of its clamp. Jim On Fri, 9 Oct 2009, Mary Tang wrote: > Hi all -- > > > We really need to get back to this question of how we are going to > accommodate requests for metal-containing materials in clean dry etch > tools. This request strikes me as being an incremental step in that > direction.... > > > As for as lampoly is concerned (and I suspect would also apply to > P5000etch), this seems reasonable. The EBR margin should be sufficient > (a wafer without EBR risks sticking to the lampoly clamp ring.) And the > clamp is made from alumina, so I don't think there's an appreciable > contamination risk from whatever trace Al may remain on exposed wafer > surfaces. > > > I vote that we OK this request -- with the proviso that we update the > documentation to describe in detail the rationale and conditions under > which semi-clean wafers can be processed in lampoly (and p5000etch.) > > > So... do we have a quorum? > > > > Mary > > Nahid Harjee wrote: > > SpecMat, > > > > I am designing a process to fabricate single crystal silicon > > cantilevers that are 3 um thick. The narrowest cantilevers are 14 um > > wide and have 4 "legs" at the clamped end that are 2 um wide. I am > > trying to select a tool to etch the 3 um of silicon to define the > > cantilever that will produce straight sidewalls. In the past, I have > > used stsetch to define wider cantilevers. However, I am concerned that > > the scalloping resulting from this tool will make it difficult to etch > > the 2 um legs of the new design. Thus, I am writing to propose that I > > perform this etch with HBr/Cl2 chemistry in lampoly or p5000. What > > makes this process non-standard is that my wafers will be semi-clean > > at this point. The step prior to defining the cantilevers is > > deposition of 1500 A of Al in gryphon which is then patterned with a > > wet etch in Al-11. During the Si etch, the Al will never be exposed to > > the plasma (it will be covered by 3 um of resist). However, there is a > > chance that there will be trace Al on the exposed Si from the Al-11 > > bath. At the most recent process clinic, Keith Best raised the point > > that there may be exposed Al in the EBR region of my wafers. In order > > to minimize this possibility, I can use 5 mm EBR for the Al litho and > > 2 mm EBR for the cantilever litho, ensuring there's a buffer of 3 mm > > of resist with no Al below it. > > > > I look foward to hearing your decision on the proposed process or if > > there is a tool that is better suited for this process, I welcome any > > suggestions. > > > > Thanks, > > > > nh > > > > -- > > Nahid Harjee > > Ph.D. Candidate > > Electrical Engineering > > Stanford University > > 408-761-8651 > > > -- -------------------------------------------------------------- James (Jim) P. McVittie, Ph.D. Sr. Research Scientist Paul G. Allen Building Electrical Engineering Stanford Nanofabrication Facility jmcvittie at stanford.edu Stanford University Office: (650) 725-3640 Rm. 336X, 330 Serra Mall Lab: (650) 721-6834 Stanford, CA 94305-4075 Fax: (650) 723-4659 From edmyers at stanford.edu Fri Oct 9 10:47:30 2009 From: edmyers at stanford.edu (Ed Myers) Date: Fri, 09 Oct 2009 10:47:30 -0700 Subject: SiO2 deposition in innotec ebeam evaporator In-Reply-To: <4ACF62DC.3040003@stanford.edu> References: <521462444.6894251252455785038.JavaMail.root@zm08.stanford.edu> <4ACF62DC.3040003@stanford.edu> Message-ID: <6.2.5.6.2.20091009104711.0535d7e8@stanford.edu> Yes, I exchanged emails with him a month ago. Ed At 09:20 AM 10/9/2009, Mary Tang wrote: >Hi all - > >Did we ever get back to this person? > >Mary > >Min-Kyo Seo wrote: >>Dear Spec Mat panel, >> >>I am a postdoc in the group of Mark Brongersma in the MSE department. >> >>I would like to ask about innotec ebeam evaporator. >>Can I perform SiO2 deposition? >> >>All the best, >>Min-Kyo Seo >>----------------------------------------------------------------------------- >>Postdoctoral Scholar >>Mark Brongersma's Group >>Department of Materials Science and Engineering >>McCollough Building #216 >>Stanford University >>Cell: (650)353-0614 Fax: (650)724-9851 >>E-mail: mkseo at stanford.edu; minkyo.seo at gmail.com >> >> > > >-- >Mary X. Tang, Ph.D. >Stanford Nanofabrication Facility >CIS Room 136, Mail Code 4070 >Stanford, CA 94305 >(650)723-9980 >mtang at stanford.edu >http://snf.stanford.edu From edmyers at stanford.edu Fri Oct 9 10:48:27 2009 From: edmyers at stanford.edu (Ed Myers) Date: Fri, 09 Oct 2009 10:48:27 -0700 Subject: TXRF results for continued processing on semi-clean tools... In-Reply-To: <4ACF62FA.6080200@stanford.edu> References: <3F24868DDBDC7B46B2289E33B58C4CB11F5DDE5118@QUSWAMI-DSRV1.quswami.local> <4ACF62FA.6080200@stanford.edu> Message-ID: <6.2.5.6.2.20091009104743.0536f3f8@stanford.edu> Likewise, I've talked with Robert regarding this request. He is not certain he needs the system, and he won't if we get the new 610's in. Ed At 09:21 AM 10/9/2009, Mary Tang wrote: >And Robert? > >Mary > >Robert Huang wrote: >> >>Dear SNF Specmat Committee Members: >> >> >> >>I would like to ask for the committee's approval to run 4" silicon >>wafers on SNF semi-clean tools (mainly the AG4100 RTA machine) that >>have been deposited with titanium oxide via e-beam evaporation >>through an external vendor. We have worked with this vendor to >>reduce metal contamination levels below the 1e12/cm2 "semi-clean" >>specification limit. As you will see in the attached file, prior >>to taking corrective action, there were locations on a test wafer >>that clearly exhibited Fe and Cu levels above the 1e12/cm2 >>limit. However, after detailed investigation, several steps were >>taken to clean up the tool with the positive results shown in the >>attached file from the last test wafer. Note that the TXRF results >>were provided by Evans Analytical Group (EAG) using a W source >>which can detect elements from S-Zn and Mo-Hf. If an element is >>not listed in the table, it was not detected in the >>analysis. Evans has a detailed procedure for calibration of their >>TXRF equipment and guarantee reproducibility to within the reported >>results (uncertainty values in the table are 1sigma standard >>deviations) through use of calibrated Vanadium and Nickel >>references. Also note that due to overlap in emission energies, >>EAG can only report upper bounds for some of the elements >>(specifically the Cu and Hf energy peaks overlap) and the >>background matrix Ti energy peak interferes with the Cl, K, and Ca peaks. >> >> >> >>If there are any questions, please do not hesitate to contact me. >> >> >> >>Sincerely, >> >> >> >>Robert Huang >> >>Director, Process and Device Technology >> >>QuSwami, Inc. >> >>505 Montgomery St., Suite 300 >> >>San Francisco, CA 94111 >> >>415-834-9910 (Office) >> >>408-854-0450 (Cell) >> >>roberth at quswami.com > > >-- >Mary X. Tang, Ph.D. >Stanford Nanofabrication Facility >CIS Room 136, Mail Code 4070 >Stanford, CA 94305 >(650)723-9980 >mtang at stanford.edu >http://snf.stanford.edu From edmyers at stanford.edu Fri Oct 9 11:29:35 2009 From: edmyers at stanford.edu (Ed Myers) Date: Fri, 09 Oct 2009 11:29:35 -0700 Subject: Request to use lampoly or p5000 to etch semi-clean wafers In-Reply-To: References: <4ACF5AD9.2070204@stanford.edu> Message-ID: <6.2.5.6.2.20091009112909.035cde90@stanford.edu> It's OK with me, but we should let Nancy chime in. At 10:07 AM 10/9/2009, Jim McVittie wrote: >Mary, > >Back at the beginning of time, we wanted to keep all metals of the Lam and >push requests like this to the P5000. The idea was to reserve the Lam for >frontend processes where being metal free is most important. However, yrs >back when we did TXRF measurements on the Lam, we found that it was no >better then the P5000 Si chamber and the key was the post etch cleaning. >So I do not think it make much difference from a metal contamination >viewpoint whether this work is done in the Lam or P5000. Since this is not >a high resolution etch, I would recommand he use the P-5000. By the way, >the Lam intrically has Al comtamination because of its clamp. > > Jim > >On Fri, 9 Oct 2009, Mary Tang wrote: > > > Hi all -- > > > > > > We really need to get back to this question of how we are going to > > accommodate requests for metal-containing materials in clean dry etch > > tools. This request strikes me as being an incremental step in that > > direction.... > > > > > > As for as lampoly is concerned (and I suspect would also apply to > > P5000etch), this seems reasonable. The EBR margin should be sufficient > > (a wafer without EBR risks sticking to the lampoly clamp ring.) And the > > clamp is made from alumina, so I don't think there's an appreciable > > contamination risk from whatever trace Al may remain on exposed wafer > > surfaces. > > > > > > I vote that we OK this request -- with the proviso that we update the > > documentation to describe in detail the rationale and conditions under > > which semi-clean wafers can be processed in lampoly (and p5000etch.) > > > > > > So... do we have a quorum? > > > > > > > > Mary > > > > Nahid Harjee wrote: > > > SpecMat, > > > > > > I am designing a process to fabricate single crystal silicon > > > cantilevers that are 3 um thick. The narrowest cantilevers are 14 um > > > wide and have 4 "legs" at the clamped end that are 2 um wide. I am > > > trying to select a tool to etch the 3 um of silicon to define the > > > cantilever that will produce straight sidewalls. In the past, I have > > > used stsetch to define wider cantilevers. However, I am concerned that > > > the scalloping resulting from this tool will make it difficult to etch > > > the 2 um legs of the new design. Thus, I am writing to propose that I > > > perform this etch with HBr/Cl2 chemistry in lampoly or p5000. What > > > makes this process non-standard is that my wafers will be semi-clean > > > at this point. The step prior to defining the cantilevers is > > > deposition of 1500 A of Al in gryphon which is then patterned with a > > > wet etch in Al-11. During the Si etch, the Al will never be exposed to > > > the plasma (it will be covered by 3 um of resist). However, there is a > > > chance that there will be trace Al on the exposed Si from the Al-11 > > > bath. At the most recent process clinic, Keith Best raised the point > > > that there may be exposed Al in the EBR region of my wafers. In order > > > to minimize this possibility, I can use 5 mm EBR for the Al litho and > > > 2 mm EBR for the cantilever litho, ensuring there's a buffer of 3 mm > > > of resist with no Al below it. > > > > > > I look foward to hearing your decision on the proposed process or if > > > there is a tool that is better suited for this process, I welcome any > > > suggestions. > > > > > > Thanks, > > > > > > nh > > > > > > -- > > > Nahid Harjee > > > Ph.D. Candidate > > > Electrical Engineering > > > Stanford University > > > 408-761-8651 > > > > > > > >-- >-------------------------------------------------------------- >James (Jim) P. McVittie, Ph.D. Sr. Research Scientist >Paul G. Allen Building Electrical Engineering >Stanford Nanofabrication Facility jmcvittie at stanford.edu >Stanford University Office: (650) 725-3640 >Rm. 336X, 330 Serra Mall Lab: (650) 721-6834 >Stanford, CA 94305-4075 Fax: (650) 723-4659 From nlatta at stanford.edu Fri Oct 9 11:44:21 2009 From: nlatta at stanford.edu (Nancy Latta) Date: Fri, 09 Oct 2009 11:44:21 -0700 Subject: Request to use lampoly or p5000 to etch semi-clean wafers In-Reply-To: <6.2.5.6.2.20091009112909.035cde90@stanford.edu> References: <4ACF5AD9.2070204@stanford.edu> <6.2.5.6.2.20091009112909.035cde90@stanford.edu> Message-ID: <4ACF8485.6050407@stanford.edu> I am ok with this request. I am also ok with Nahid using either tool...... -Nancy Ed Myers wrote: > It's OK with me, but we should let Nancy chime in. > > At 10:07 AM 10/9/2009, Jim McVittie wrote: >> Mary, >> >> Back at the beginning of time, we wanted to keep all metals of the >> Lam and >> push requests like this to the P5000. The idea was to reserve the Lam >> for >> frontend processes where being metal free is most important. However, >> yrs >> back when we did TXRF measurements on the Lam, we found that it was no >> better then the P5000 Si chamber and the key was the post etch cleaning. >> So I do not think it make much difference from a metal contamination >> viewpoint whether this work is done in the Lam or P5000. Since this >> is not >> a high resolution etch, I would recommand he use the P-5000. By the way, >> the Lam intrically has Al comtamination because of its clamp. >> >> Jim >> >> On Fri, 9 Oct 2009, Mary Tang wrote: >> >> > Hi all -- >> > >> > >> > We really need to get back to this question of how we are going to >> > accommodate requests for metal-containing materials in clean dry etch >> > tools. This request strikes me as being an incremental step in that >> > direction.... >> > >> > >> > As for as lampoly is concerned (and I suspect would also apply to >> > P5000etch), this seems reasonable. The EBR margin should be >> sufficient >> > (a wafer without EBR risks sticking to the lampoly clamp ring.) >> And the >> > clamp is made from alumina, so I don't think there's an appreciable >> > contamination risk from whatever trace Al may remain on exposed wafer >> > surfaces. >> > >> > >> > I vote that we OK this request -- with the proviso that we update the >> > documentation to describe in detail the rationale and conditions under >> > which semi-clean wafers can be processed in lampoly (and p5000etch.) >> > >> > >> > So... do we have a quorum? >> > >> > >> > >> > Mary >> > >> > Nahid Harjee wrote: >> > > SpecMat, >> > > >> > > I am designing a process to fabricate single crystal silicon >> > > cantilevers that are 3 um thick. The narrowest cantilevers are 14 um >> > > wide and have 4 "legs" at the clamped end that are 2 um wide. I am >> > > trying to select a tool to etch the 3 um of silicon to define the >> > > cantilever that will produce straight sidewalls. In the past, I have >> > > used stsetch to define wider cantilevers. However, I am concerned >> that >> > > the scalloping resulting from this tool will make it difficult to >> etch >> > > the 2 um legs of the new design. Thus, I am writing to propose >> that I >> > > perform this etch with HBr/Cl2 chemistry in lampoly or p5000. What >> > > makes this process non-standard is that my wafers will be semi-clean >> > > at this point. The step prior to defining the cantilevers is >> > > deposition of 1500 A of Al in gryphon which is then patterned with a >> > > wet etch in Al-11. During the Si etch, the Al will never be >> exposed to >> > > the plasma (it will be covered by 3 um of resist). However, there >> is a >> > > chance that there will be trace Al on the exposed Si from the Al-11 >> > > bath. At the most recent process clinic, Keith Best raised the point >> > > that there may be exposed Al in the EBR region of my wafers. In >> order >> > > to minimize this possibility, I can use 5 mm EBR for the Al litho >> and >> > > 2 mm EBR for the cantilever litho, ensuring there's a buffer of 3 mm >> > > of resist with no Al below it. >> > > >> > > I look foward to hearing your decision on the proposed process or if >> > > there is a tool that is better suited for this process, I welcome >> any >> > > suggestions. >> > > >> > > Thanks, >> > > >> > > nh >> > > >> > > -- >> > > Nahid Harjee >> > > Ph.D. Candidate >> > > Electrical Engineering >> > > Stanford University >> > > 408-761-8651 >> > >> > >> > >> >> -- >> -------------------------------------------------------------- >> James (Jim) P. McVittie, Ph.D. Sr. Research Scientist >> Paul G. Allen Building Electrical Engineering >> Stanford Nanofabrication Facility jmcvittie at stanford.edu >> Stanford University Office: (650) 725-3640 >> Rm. 336X, 330 Serra Mall Lab: (650) 721-6834 >> Stanford, CA 94305-4075 Fax: (650) 723-4659 > > From mtang at stanford.edu Fri Oct 9 11:51:20 2009 From: mtang at stanford.edu (Mary Tang) Date: Fri, 09 Oct 2009 11:51:20 -0700 Subject: Request to use lampoly or p5000 to etch semi-clean wafers In-Reply-To: <4ACF8485.6050407@stanford.edu> References: <4ACF5AD9.2070204@stanford.edu> <6.2.5.6.2.20091009112909.035cde90@stanford.edu> <4ACF8485.6050407@stanford.edu> Message-ID: <4ACF8628.8090609@stanford.edu> I agree with Nancy. So, I take it we're all OK with this? I'll let Nahid know. Thanks all! Mary Nancy Latta wrote: > I am ok with this request. I am also ok with Nahid using either > tool...... > > -Nancy > > Ed Myers wrote: >> It's OK with me, but we should let Nancy chime in. >> >> At 10:07 AM 10/9/2009, Jim McVittie wrote: >>> Mary, >>> >>> Back at the beginning of time, we wanted to keep all metals of the >>> Lam and >>> push requests like this to the P5000. The idea was to reserve the >>> Lam for >>> frontend processes where being metal free is most important. >>> However, yrs >>> back when we did TXRF measurements on the Lam, we found that it was no >>> better then the P5000 Si chamber and the key was the post etch >>> cleaning. >>> So I do not think it make much difference from a metal contamination >>> viewpoint whether this work is done in the Lam or P5000. Since this >>> is not >>> a high resolution etch, I would recommand he use the P-5000. By the >>> way, >>> the Lam intrically has Al comtamination because of its clamp. >>> >>> Jim >>> >>> On Fri, 9 Oct 2009, Mary Tang wrote: >>> >>> > Hi all -- >>> > >>> > >>> > We really need to get back to this question of how we are going to >>> > accommodate requests for metal-containing materials in clean dry etch >>> > tools. This request strikes me as being an incremental step in that >>> > direction.... >>> > >>> > >>> > As for as lampoly is concerned (and I suspect would also apply to >>> > P5000etch), this seems reasonable. The EBR margin should be >>> sufficient >>> > (a wafer without EBR risks sticking to the lampoly clamp ring.) >>> And the >>> > clamp is made from alumina, so I don't think there's an appreciable >>> > contamination risk from whatever trace Al may remain on exposed wafer >>> > surfaces. >>> > >>> > >>> > I vote that we OK this request -- with the proviso that we update the >>> > documentation to describe in detail the rationale and conditions >>> under >>> > which semi-clean wafers can be processed in lampoly (and p5000etch.) >>> > >>> > >>> > So... do we have a quorum? >>> > >>> > >>> > >>> > Mary >>> > >>> > Nahid Harjee wrote: >>> > > SpecMat, >>> > > >>> > > I am designing a process to fabricate single crystal silicon >>> > > cantilevers that are 3 um thick. The narrowest cantilevers are >>> 14 um >>> > > wide and have 4 "legs" at the clamped end that are 2 um wide. I am >>> > > trying to select a tool to etch the 3 um of silicon to define the >>> > > cantilever that will produce straight sidewalls. In the past, I >>> have >>> > > used stsetch to define wider cantilevers. However, I am >>> concerned that >>> > > the scalloping resulting from this tool will make it difficult >>> to etch >>> > > the 2 um legs of the new design. Thus, I am writing to propose >>> that I >>> > > perform this etch with HBr/Cl2 chemistry in lampoly or p5000. What >>> > > makes this process non-standard is that my wafers will be >>> semi-clean >>> > > at this point. The step prior to defining the cantilevers is >>> > > deposition of 1500 A of Al in gryphon which is then patterned >>> with a >>> > > wet etch in Al-11. During the Si etch, the Al will never be >>> exposed to >>> > > the plasma (it will be covered by 3 um of resist). However, >>> there is a >>> > > chance that there will be trace Al on the exposed Si from the Al-11 >>> > > bath. At the most recent process clinic, Keith Best raised the >>> point >>> > > that there may be exposed Al in the EBR region of my wafers. In >>> order >>> > > to minimize this possibility, I can use 5 mm EBR for the Al >>> litho and >>> > > 2 mm EBR for the cantilever litho, ensuring there's a buffer of >>> 3 mm >>> > > of resist with no Al below it. >>> > > >>> > > I look foward to hearing your decision on the proposed process >>> or if >>> > > there is a tool that is better suited for this process, I >>> welcome any >>> > > suggestions. >>> > > >>> > > Thanks, >>> > > >>> > > nh >>> > > >>> > > -- >>> > > Nahid Harjee >>> > > Ph.D. Candidate >>> > > Electrical Engineering >>> > > Stanford University >>> > > 408-761-8651 >>> > >>> > >>> > >>> >>> -- >>> -------------------------------------------------------------- >>> James (Jim) P. McVittie, Ph.D. Sr. Research Scientist >>> Paul G. Allen Building Electrical Engineering >>> Stanford Nanofabrication Facility jmcvittie at stanford.edu >>> Stanford University Office: (650) 725-3640 >>> Rm. 336X, 330 Serra Mall Lab: (650) 721-6834 >>> Stanford, CA 94305-4075 Fax: (650) 723-4659 >> >> > > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Fri Oct 9 12:00:16 2009 From: mtang at stanford.edu (Mary Tang) Date: Fri, 09 Oct 2009 12:00:16 -0700 Subject: Request to use lampoly or p5000 to etch semi-clean wafers In-Reply-To: <2feeb6700910082108gfec52f5xec57f35c3afb0afd@mail.gmail.com> References: <2feeb6700910082108gfec52f5xec57f35c3afb0afd@mail.gmail.com> Message-ID: <4ACF8840.8090005@stanford.edu> Hi Nahid -- It's agreed, your request is approved for both the poly etch chamber in p5000etch and in lampoly, with the EBR considerations you describe. Thanks! Mary Nahid Harjee wrote: > SpecMat, > > I am designing a process to fabricate single crystal silicon > cantilevers that are 3 um thick. The narrowest cantilevers are 14 um > wide and have 4 "legs" at the clamped end that are 2 um wide. I am > trying to select a tool to etch the 3 um of silicon to define the > cantilever that will produce straight sidewalls. In the past, I have > used stsetch to define wider cantilevers. However, I am concerned that > the scalloping resulting from this tool will make it difficult to etch > the 2 um legs of the new design. Thus, I am writing to propose that I > perform this etch with HBr/Cl2 chemistry in lampoly or p5000. What > makes this process non-standard is that my wafers will be semi-clean > at this point. The step prior to defining the cantilevers is > deposition of 1500 A of Al in gryphon which is then patterned with a > wet etch in Al-11. During the Si etch, the Al will never be exposed to > the plasma (it will be covered by 3 um of resist). However, there is a > chance that there will be trace Al on the exposed Si from the Al-11 > bath. At the most recent process clinic, Keith Best raised the point > that there may be exposed Al in the EBR region of my wafers. In order > to minimize this possibility, I can use 5 mm EBR for the Al litho and > 2 mm EBR for the cantilever litho, ensuring there's a buffer of 3 mm > of resist with no Al below it. > > I look foward to hearing your decision on the proposed process or if > there is a tool that is better suited for this process, I welcome any > suggestions. > > Thanks, > > nh > > -- > Nahid Harjee > Ph.D. Candidate > Electrical Engineering > Stanford University > 408-761-8651 -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From nharjee at stanford.edu Fri Oct 9 12:55:49 2009 From: nharjee at stanford.edu (Nahid Harjee) Date: Fri, 9 Oct 2009 12:55:49 -0700 Subject: Request to use lampoly or p5000 to etch semi-clean wafers In-Reply-To: <4ACF8840.8090005@stanford.edu> References: <2feeb6700910082108gfec52f5xec57f35c3afb0afd@mail.gmail.com> <4ACF8840.8090005@stanford.edu> Message-ID: <2feeb6700910091255h1e7c794dm9074c1d94dc040bd@mail.gmail.com> Thanks for the prompt reply. nh On Fri, Oct 9, 2009 at 12:00 PM, Mary Tang wrote: > Hi Nahid -- > > It's agreed, your request is approved for both the poly etch chamber in > p5000etch and in lampoly, with the EBR considerations you describe. > > Thanks! > > Mary > > > Nahid Harjee wrote: > >> SpecMat, >> >> I am designing a process to fabricate single crystal silicon cantilevers >> that are 3 um thick. The narrowest cantilevers are 14 um wide and have 4 >> "legs" at the clamped end that are 2 um wide. I am trying to select a tool >> to etch the 3 um of silicon to define the cantilever that will produce >> straight sidewalls. In the past, I have used stsetch to define wider >> cantilevers. However, I am concerned that the scalloping resulting from this >> tool will make it difficult to etch the 2 um legs of the new design. Thus, I >> am writing to propose that I perform this etch with HBr/Cl2 chemistry in >> lampoly or p5000. What makes this process non-standard is that my wafers >> will be semi-clean at this point. The step prior to defining the cantilevers >> is deposition of 1500 A of Al in gryphon which is then patterned with a wet >> etch in Al-11. During the Si etch, the Al will never be exposed to the >> plasma (it will be covered by 3 um of resist). However, there is a chance >> that there will be trace Al on the exposed Si from the Al-11 bath. At the >> most recent process clinic, Keith Best raised the point that there may be >> exposed Al in the EBR region of my wafers. In order to minimize this >> possibility, I can use 5 mm EBR for the Al litho and 2 mm EBR for the >> cantilever litho, ensuring there's a buffer of 3 mm of resist with no Al >> below it. >> >> I look foward to hearing your decision on the proposed process or if there >> is a tool that is better suited for this process, I welcome any suggestions. >> >> Thanks, >> >> nh >> >> -- >> Nahid Harjee >> Ph.D. Candidate >> Electrical Engineering >> Stanford University >> 408-761-8651 >> > > > -- > Mary X. Tang, Ph.D. > Stanford Nanofabrication Facility > CIS Room 136, Mail Code 4070 > Stanford, CA 94305 > (650)723-9980 > mtang at stanford.edu > http://snf.stanford.edu > > -- Nahid Harjee Ph.D. Candidate Electrical Engineering Stanford University 408-761-8651 -------------- next part -------------- An HTML attachment was scrubbed... URL: From chienyuc at stanford.edu Wed Oct 14 12:21:46 2009 From: chienyuc at stanford.edu (Chien-Yu Chen) Date: Wed, 14 Oct 2009 12:21:46 -0700 (PDT) Subject: Ask about perfluorinated solvent In-Reply-To: <443304488.3958221255548014506.JavaMail.root@zm03.stanford.edu> Message-ID: <1961141832.3958811255548106622.JavaMail.root@zm03.stanford.edu> Hi, I'm planning a process that may involve the DuPont Teflon AF (amorphous fluropolymer). ?I was told that the Teflon AF is an approved material in SNF, while no related solvent found approved on the website list. ?Specifically, the perfluorinated solvent I'm searching for are the 3M Flourinert series, FC-72, FC-75, or FC-77, as suggests from the DuPont Teflon AF Processing and Use Guide [1]. The major purposes of requesting this solvent are to dilute and to remove Teflon films on standard Si wafers. ?The equipments may involved in are wbsolvent and headway2. ?Please inform me if these solvent are already approved or any applications need to be done. ?Thanks for your help. Best regards, Chien-Yu Chen Coral login: chienyuc [1]Dupont Teflon AF Processing and Use Guide http://www2.dupont.com/Teflon_Industrial/en_US/assets/downloads/h44015.pdf [2]FC-72 detail(with MSDS datasheet available there, CAS 86508-42-1) http://products3.3m.com/catalog/us/en001/oil_gas/specialty_materials/node_2KJ8NGV19Gbe/root_GST1T4S9TCgv/vroot_G1F6DNZDBVge/gvel_X65PZNZ1SHgl/theme_us_oilgas_3_0/command_AbcPageHandler/output_html From mtang at stanford.edu Wed Oct 14 15:22:02 2009 From: mtang at stanford.edu (Mary Tang) Date: Wed, 14 Oct 2009 15:22:02 -0700 Subject: Ask about perfluorinated solvent In-Reply-To: <1961141832.3958811255548106622.JavaMail.root@zm03.stanford.edu> References: <1961141832.3958811255548106622.JavaMail.root@zm03.stanford.edu> Message-ID: <4AD64F0A.20701@stanford.edu> Hi Chien-Yu -- Yes, Teflon AF has been approved for limited use in the lab. Could you please provide some additional details as to the experiments you'd like to do? In other words" What kind of volumes will be used? How do you plan to dispose of waste and do you need to store unused chemical? Where do you plan to process your wafers afterwards? Do you require a hot plate? One concern about using liquid fluoropolymer in the litho area is the very real possibility that it will drip or spray onto surrounding surfaces or wafer handling tools and then will be picked up and transferred with the touch of a glove. Resist doesn't stick well to this stuff, so this could result in lifting for other people. Although chemicals like this have been allowed at headway2, be prepared for some additional training on handling special chemicals like this at this station. Mary Chien-Yu Chen wrote: > Hi, > > I'm planning a process that may involve the DuPont Teflon AF (amorphous fluropolymer). I was told that the Teflon AF is an approved material in SNF, while no related solvent found approved on the website list. Specifically, the perfluorinated solvent I'm searching for are the 3M Flourinert series, FC-72, FC-75, or FC-77, as suggests from the DuPont Teflon AF Processing and Use Guide [1]. > > The major purposes of requesting this solvent are to dilute and to remove Teflon films on standard Si wafers. The equipments may involved in are wbsolvent and headway2. Please inform me if these solvent are already approved or any applications need to be done. Thanks for your help. > > > Best regards, > Chien-Yu Chen > Coral login: chienyuc > > [1]Dupont Teflon AF Processing and Use Guide > http://www2.dupont.com/Teflon_Industrial/en_US/assets/downloads/h44015.pdf > > [2]FC-72 detail(with MSDS datasheet available there, CAS 86508-42-1) > http://products3.3m.com/catalog/us/en001/oil_gas/specialty_materials/node_2KJ8NGV19Gbe/root_GST1T4S9TCgv/vroot_G1F6DNZDBVge/gvel_X65PZNZ1SHgl/theme_us_oilgas_3_0/command_AbcPageHandler/output_html > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Fri Oct 23 16:32:10 2009 From: mtang at stanford.edu (Mary Tang) Date: Fri, 23 Oct 2009 16:32:10 -0700 Subject: [Fwd: Re: UC Berkeley processing- details] Message-ID: <4AE23CFA.9020001@stanford.edu> Hi all -- Another request from Berkeley for semiclean 6" processing of stoichiometric nitride. This prospective labmember would like to process this next week. Do you all think we can or should reclassify thermconitride in time for this? Mary -------- Original Message -------- Subject: Re: UC Berkeley processing- details Date: Fri, 23 Oct 2009 16:15:43 -0700 From: Anupama Bowonder Organization: UC Berkeley To: Mary Tang References: <4AE22657.5060309 at eecs.berkeley.edu> <4AE22FC8.5040208 at stanford.edu> Hi Mary, I just took a look at my split sheet again to confirm and so I have some splits with High K (Al2O3) + Poly Si Ge gates all processed MOS clean thus far. SO both the Poly SIGe gate and the gate dielectric beneath would be possibly attacked by piranha. I just realized since SNF does do a lot of Ge with Al2O3 dielectrics there is probably already a bench for processing these wafers? Since Berkeley is still new to these materials we have a seperate sink here for Ge and High K processing where we do a Acetone and EGBHF clean of the wafers and then use seperate boats specifically for these wafers. I am sure SNF has a more sophisticated way to deal with these materials in a furnace. Thanks for all your time and help! Anupama -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From edmyers at stanford.edu Mon Oct 26 08:26:58 2009 From: edmyers at stanford.edu (Ed Myers) Date: Mon, 26 Oct 2009 08:26:58 -0700 Subject: [Fwd: Re: UC Berkeley processing- details] In-Reply-To: <4AE23CFA.9020001@stanford.edu> References: <4AE23CFA.9020001@stanford.edu> Message-ID: <6.2.5.6.2.20091026082426.027e25a8@stanford.edu> Al, I think we should involve the lab members and especially Maurice. We should include poly and LTO along with the nitride in this decision. Following last years mandate, we should divide these tubes in to two categories. My bet is the lab members will nominate the new tubes for the dirtier category. Ed At 04:32 PM 10/23/2009, Mary Tang wrote: >Hi all -- > > >Another request from Berkeley for semiclean 6" processing of >stoichiometric nitride. This prospective labmember would like to >process this next week. Do you all think we can or should >reclassify thermconitride in time for this? > >Mary > > >-------- Original Message -------- >Subject: Re: UC Berkeley processing- details >Date: Fri, 23 Oct 2009 16:15:43 -0700 >From: Anupama Bowonder > >Organization: UC Berkeley >To: Mary Tang >References: ><4AE22657.5060309 at eecs.berkeley.edu> ><4AE22FC8.5040208 at stanford.edu> > > > >Hi Mary, > > I just took a look at my split sheet again to confirm and so I have >some splits with High K (Al2O3) + Poly Si Ge gates all processed MOS >clean thus far. SO both the Poly SIGe gate and the gate dielectric >beneath would be possibly attacked by piranha. I just realized since SNF >does do a lot of Ge with Al2O3 dielectrics there is probably already a >bench for processing these wafers? > >Since Berkeley is still new to these materials we have a seperate sink >here for Ge and High K processing where we do a Acetone and EGBHF clean >of the wafers and then use seperate boats specifically for these wafers. >I am sure SNF has a more sophisticated way to deal with these materials >in a furnace. > >Thanks for all your time and help! >Anupama > > >-- >Mary X. Tang, Ph.D. >Stanford Nanofabrication Facility >CIS Room 136, Mail Code 4070 >Stanford, CA 94305 >(650)723-9980 >mtang at stanford.edu >http://snf.stanford.edu From mtang at stanford.edu Mon Oct 26 08:58:34 2009 From: mtang at stanford.edu (Mary Tang) Date: Mon, 26 Oct 2009 08:58:34 -0700 Subject: [Fwd: Re: UC Berkeley processing- details] In-Reply-To: <6.2.5.6.2.20091026082426.027e25a8@stanford.edu> References: <4AE23CFA.9020001@stanford.edu> <6.2.5.6.2.20091026082426.027e25a8@stanford.edu> Message-ID: <4AE5C72A.5050004@stanford.edu> I agree. I suggest the following: Near term (next several weeks?): We come up with a proposal for what is allowed in these tubes and present to labmembers. They will throw darts and it and we can refine it. Our proposal should be well-thought out, with a clear rationale. We can use SpecMat requests as a guide. Ed, do you want to take the first stab at this? Longer term (next few months?): We start up the contamination discussions again. This time, we need to better define and focus on technical issues at hand. From the last few rounds, the issues appear to be: LPCVD of non-"clean" substrates (containing new materials, trace contaminants); RTA of non-"clean" materials (hopefully better addressed with new 610's); Cr as a hard mask ("semiclean" deposition and etching); ability to accommodate more flexible DRIE processing ("gold" contaminated substrates, substrates in which "semiclean" metals may be exposed). We will also need to figure out how to better accommodate GaAs epi, Ge epi and nanowire device research. Mary Ed Myers wrote: > Al, > > I think we should involve the lab members and especially Maurice. We > should include poly and LTO along with the nitride in this decision. > Following last years mandate, we should divide these tubes in to two > categories. My bet is the lab members will nominate the new tubes for > the dirtier category. > > Ed > > At 04:32 PM 10/23/2009, Mary Tang wrote: >> Hi all -- >> >> >> Another request from Berkeley for semiclean 6" processing of >> stoichiometric nitride. This prospective labmember would like to >> process this next week. Do you all think we can or should reclassify >> thermconitride in time for this? >> >> Mary >> >> >> -------- Original Message -------- >> Subject: Re: UC Berkeley processing- details >> Date: Fri, 23 Oct 2009 16:15:43 -0700 >> From: Anupama Bowonder >> >> Organization: UC Berkeley >> To: Mary Tang >> References: >> <4AE22657.5060309 at eecs.berkeley.edu> >> <4AE22FC8.5040208 at stanford.edu> >> >> >> >> Hi Mary, >> >> I just took a look at my split sheet again to confirm and so I have >> some splits with High K (Al2O3) + Poly Si Ge gates all processed MOS >> clean thus far. SO both the Poly SIGe gate and the gate dielectric >> beneath would be possibly attacked by piranha. I just realized since SNF >> does do a lot of Ge with Al2O3 dielectrics there is probably already a >> bench for processing these wafers? >> >> Since Berkeley is still new to these materials we have a seperate sink >> here for Ge and High K processing where we do a Acetone and EGBHF clean >> of the wafers and then use seperate boats specifically for these wafers. >> I am sure SNF has a more sophisticated way to deal with these materials >> in a furnace. >> >> Thanks for all your time and help! >> Anupama >> >> >> -- >> Mary X. Tang, Ph.D. >> Stanford Nanofabrication Facility >> CIS Room 136, Mail Code 4070 >> Stanford, CA 94305 >> (650)723-9980 >> mtang at stanford.edu >> http://snf.stanford.edu > > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Tue Oct 27 16:37:24 2009 From: mtang at stanford.edu (Mary Tang) Date: Tue, 27 Oct 2009 16:37:24 -0700 Subject: [Fwd: Spin-on transparent conductive layer] Message-ID: <4AE78434.8050404@stanford.edu> Hi all -- Here's a request from Scott Andrews, who was a former student here so is familiar with the concerns. I think I have some reservations. We've not allowed conductive and semiconducting nanoparticles solutions at headway2 because the spray off the wafer edges will dry and the particulates will float around. These could create problems if the contaminated other people's wafers. We do allow latex nanoparticle in solution at headway2 because these are soluble in acetone and removed in sulfuric clean. This stuff contains silver so it's rather like the conducting nanoparticle problem. However, unlike CNT's and many other nanoparticles, the standard cleans will remove possible contaminants. I'm inclined to OK this, provided Scott is fully aware of the concerns and makes sure to cleanup and take appropriate precautions (he has been a conscientious labmember). Does anyone have other concerns? I also think James should be made aware of this, since headway2 is his station. What do you think? Mary -------- Original Message -------- Subject: Spin-on transparent conductive layer Date: Tue, 27 Oct 2009 15:07:38 -0700 From: Scott Andrews To: Mary Tang Hi Mary, We would like to use ClearOhm at the headway and hot plates. Attached are the process notes and MSDS. Has anything similar already been approved my the specmat committee? I can prep the whole package for approval, but I seem to remember when I was at Stanford that these had been tried at SNF. Please let me know if I need to go through the committee or if you expect any particular concerns. Thanks, Scott -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- A non-text attachment was scrubbed... Name: 053 ClearOhmT, Ink-N AQ (R&D Use Only).pdf Type: application/pdf Size: 56268 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Cambrios Spin-Coating Guidelines 10-09-1.pdf Type: application/pdf Size: 3956364 bytes Desc: not available URL: From edmyers at stanford.edu Wed Oct 28 07:59:54 2009 From: edmyers at stanford.edu (Ed Myers) Date: Wed, 28 Oct 2009 07:59:54 -0700 Subject: [Fwd: Spin-on transparent conductive layer] In-Reply-To: <4AE78434.8050404@stanford.edu> References: <4AE78434.8050404@stanford.edu> Message-ID: <6.2.5.6.2.20091028075725.027e6bb8@stanford.edu> I don't see why there should be an exception for this material over the other nanoparticles we have been excluding. Even if normal cleans can remove this material, we can not expect the lab members samples to be compatible with a normal clean. Ed At 04:37 PM 10/27/2009, Mary Tang wrote: >Hi all -- > >Here's a request from Scott Andrews, who was a former student here >so is familiar with the concerns. > >I think I have some reservations. We've not allowed conductive and >semiconducting nanoparticles solutions at headway2 because the spray >off the wafer edges will dry and the particulates will float >around. These could create problems if the contaminated other >people's wafers. We do allow latex nanoparticle in solution at >headway2 because these are soluble in acetone and removed in >sulfuric clean. This stuff contains silver so it's rather like the >conducting nanoparticle problem. >However, unlike CNT's and many other nanoparticles, the standard >cleans will remove possible contaminants. > >I'm inclined to OK this, provided Scott is fully aware of the >concerns and makes sure to cleanup and take appropriate >precautions (he has been a conscientious labmember). Does anyone >have other concerns? I also think James should be made aware of >this, since headway2 is his station. What do you think? > > >Mary > > > > > >-------- Original Message -------- >Subject: Spin-on transparent conductive layer >Date: Tue, 27 Oct 2009 15:07:38 -0700 >From: Scott Andrews >To: Mary Tang > > > >Hi Mary, > >We would like to use ClearOhm at the headway and hot plates. Attached >are the process notes and MSDS. Has anything similar already been >approved my the specmat committee? I can prep the whole package for >approval, but I seem to remember when I was at Stanford that these had >been tried at SNF. Please let me know if I need to go through the >committee or if you expect any particular concerns. > >Thanks, >Scott > > > > >-- >Mary X. Tang, Ph.D. >Stanford Nanofabrication Facility >CIS Room 136, Mail Code 4070 >Stanford, CA 94305 >(650)723-9980 >mtang at stanford.edu >http://snf.stanford.edu > > > >