Request to use lampoly or p5000 to etch semi-clean wafers

Nancy Latta nlatta at stanford.edu
Fri Oct 9 11:44:21 PDT 2009


I am ok with this request.  I am also ok with Nahid using either tool......

-Nancy

Ed Myers wrote:
> It's OK with me, but we should let Nancy chime in.
>
> At 10:07 AM 10/9/2009, Jim McVittie wrote:
>> Mary,
>>
>> Back at the beginning of time, we wanted to keep all metals of the 
>> Lam and
>> push requests like this to the P5000. The idea was to reserve the Lam 
>> for
>> frontend processes where being metal free is most important. However, 
>> yrs
>> back when we did TXRF measurements on the Lam, we found that it was no
>> better then the P5000 Si chamber and the key was the post etch cleaning.
>> So I do not think it make much difference from a metal contamination
>> viewpoint whether this work is done in the Lam or P5000. Since this 
>> is not
>> a high resolution etch, I would recommand he use the P-5000. By the way,
>> the Lam intrically has Al comtamination because of its clamp.
>>
>>         Jim
>>
>> On Fri, 9 Oct 2009, Mary Tang wrote:
>>
>> > Hi all --
>> >
>> >
>> > We really need to get back to this question of how we are going to
>> > accommodate requests for metal-containing materials in clean dry etch
>> > tools.  This request strikes me as being an incremental step in that
>> > direction....
>> >
>> >
>> > As for as lampoly is concerned (and I suspect would also apply to
>> > P5000etch), this seems reasonable.  The EBR margin should be 
>> sufficient
>> > (a wafer without EBR risks sticking to the lampoly clamp ring.)  
>> And the
>> > clamp is made from alumina, so I don't think there's an appreciable
>> > contamination risk from whatever trace Al may remain on exposed wafer
>> > surfaces.
>> >
>> >
>> > I vote that we OK this request -- with the proviso that we update the
>> > documentation to describe in detail the rationale and conditions under
>> > which semi-clean wafers can be processed in lampoly (and p5000etch.)
>> >
>> >
>> > So...  do we have a quorum?
>> >
>> >
>> >
>> > Mary
>> >
>> > Nahid Harjee wrote:
>> > > SpecMat,
>> > >
>> > > I am designing a process to fabricate single crystal silicon
>> > > cantilevers that are 3 um thick. The narrowest cantilevers are 14 um
>> > > wide and have 4 "legs" at the clamped end that are 2 um wide. I am
>> > > trying to select a tool to etch the 3 um of silicon to define the
>> > > cantilever that will produce straight sidewalls. In the past, I have
>> > > used stsetch to define wider cantilevers. However, I am concerned 
>> that
>> > > the scalloping resulting from this tool will make it difficult to 
>> etch
>> > > the 2 um legs of the new design. Thus, I am writing to propose 
>> that I
>> > > perform this etch with HBr/Cl2 chemistry in lampoly or p5000. What
>> > > makes this process non-standard is that my wafers will be semi-clean
>> > > at this point. The step prior to defining the cantilevers is
>> > > deposition of 1500 A of Al in gryphon which is then patterned with a
>> > > wet etch in Al-11. During the Si etch, the Al will never be 
>> exposed to
>> > > the plasma (it will be covered by 3 um of resist). However, there 
>> is a
>> > > chance that there will be trace Al on the exposed Si from the Al-11
>> > > bath. At the most recent process clinic, Keith Best raised the point
>> > > that there may be exposed Al in the EBR region of my wafers. In 
>> order
>> > > to minimize this possibility, I can use 5 mm EBR for the Al litho 
>> and
>> > > 2 mm EBR for the cantilever litho, ensuring there's a buffer of 3 mm
>> > > of resist with no Al below it.
>> > >
>> > > I look foward to hearing your decision on the proposed process or if
>> > > there is a tool that is better suited for this process, I welcome 
>> any
>> > > suggestions.
>> > >
>> > > Thanks,
>> > >
>> > > nh
>> > >
>> > > --
>> > > Nahid Harjee
>> > > Ph.D. Candidate
>> > > Electrical Engineering
>> > > Stanford University
>> > > 408-761-8651
>> >
>> >
>> >
>>
>> -- 
>> --------------------------------------------------------------
>> James (Jim) P. McVittie, Ph.D.          Sr. Research Scientist
>> Paul G. Allen Building                  Electrical Engineering
>> Stanford Nanofabrication Facility       jmcvittie at stanford.edu
>> Stanford University                     Office: (650) 725-3640
>> Rm. 336X, 330 Serra Mall                Lab: (650) 721-6834
>> Stanford, CA 94305-4075                 Fax: (650) 723-4659
>
>





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