[Fwd: Re: UC Berkeley processing- details]
mtang at stanford.edu
Mon Oct 26 08:58:34 PDT 2009
I agree. I suggest the following:
Near term (next several weeks?): We come up with a proposal for what is
allowed in these tubes and present to labmembers. They will throw darts
and it and we can refine it. Our proposal should be well-thought out,
with a clear rationale. We can use SpecMat requests as a guide. Ed, do
you want to take the first stab at this?
Longer term (next few months?): We start up the contamination
discussions again. This time, we need to better define and focus on
technical issues at hand. From the last few rounds, the issues appear
to be: LPCVD of non-"clean" substrates (containing new materials, trace
contaminants); RTA of non-"clean" materials (hopefully better addressed
with new 610's); Cr as a hard mask ("semiclean" deposition and etching);
ability to accommodate more flexible DRIE processing ("gold"
contaminated substrates, substrates in which "semiclean" metals may be
exposed). We will also need to figure out how to better accommodate
GaAs epi, Ge epi and nanowire device research.
Ed Myers wrote:
> I think we should involve the lab members and especially Maurice. We
> should include poly and LTO along with the nitride in this decision.
> Following last years mandate, we should divide these tubes in to two
> categories. My bet is the lab members will nominate the new tubes for
> the dirtier category.
> At 04:32 PM 10/23/2009, Mary Tang wrote:
>> Hi all --
>> Another request from Berkeley for semiclean 6" processing of
>> stoichiometric nitride. This prospective labmember would like to
>> process this next week. Do you all think we can or should reclassify
>> thermconitride in time for this?
>> -------- Original Message --------
>> Subject: Re: UC Berkeley processing- details
>> Date: Fri, 23 Oct 2009 16:15:43 -0700
>> From: Anupama Bowonder
>> <mailto:bowonder at eecs.berkeley.edu><bowonder at eecs.berkeley.edu>
>> Organization: UC Berkeley
>> To: Mary Tang <mailto:mtang at stanford.edu><mtang at stanford.edu>
>> <mailto:4AE22657.5060309 at eecs.berkeley.edu><4AE22657.5060309 at eecs.berkeley.edu>
>> <mailto:4AE22FC8.5040208 at stanford.edu><4AE22FC8.5040208 at stanford.edu>
>> Hi Mary,
>> I just took a look at my split sheet again to confirm and so I have
>> some splits with High K (Al2O3) + Poly Si Ge gates all processed MOS
>> clean thus far. SO both the Poly SIGe gate and the gate dielectric
>> beneath would be possibly attacked by piranha. I just realized since SNF
>> does do a lot of Ge with Al2O3 dielectrics there is probably already a
>> bench for processing these wafers?
>> Since Berkeley is still new to these materials we have a seperate sink
>> here for Ge and High K processing where we do a Acetone and EGBHF clean
>> of the wafers and then use seperate boats specifically for these wafers.
>> I am sure SNF has a more sophisticated way to deal with these materials
>> in a furnace.
>> Thanks for all your time and help!
>> Mary X. Tang, Ph.D.
>> Stanford Nanofabrication Facility
>> CIS Room 136, Mail Code 4070
>> Stanford, CA 94305
>> <mailto:mtang at stanford.edu>mtang at stanford.edu
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
mtang at stanford.edu
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