completion of partially processed wafers
carini at slac.stanford.edu
Mon Oct 3 16:44:35 PDT 2011
Thanks! I'll probably start processing by the end of this week :)
On Oct 3, 2011, at 4:27 PM, Mary Tang wrote:
> Hi Gabriella --
> Apologies for the delay in response. As we've discussed, it should be
> fine to process these wafers as you propose in semiclean tools.
> On 9/26/2011 2:18 PM, Carini, Gabriella wrote:
>> I recently joined SLAC and became SNF labmember. As in my previous position at BNL, I am involved with semiconductor processing for x-ray detectors and as I moved here I would like to have the possibility to complete 4 wafers I had started processing sometime ago at BNL. The devices I'm trying to complete at SNF have been designed and developed at BNL for the XPP instrument at LCLS (SLAC). We call them XAMPS (X-ray Active Matrix Pixel Sensor). Up to their current status the wafers have been entirely processed at BNL, Instrumentation Division, Semiconductor Detector Development and Processing Lab. This is a small class-100 cleanroom (600 sq ft) entirely developed for the fabrication of silicon detectors. These devices are made on high-resistivity (>4kOhm cm) silicon wafers (FZ). To maintain the quality and achieve the needed performances a strict control of contaminants is implemented and most of the tools are custom-made to avoid damages during wafer handling: in fact all the devices require double-side processing. Only qualified stuff members are allowed to work in this cleanroom (no more than 2 people simultaneously and 4-5 overall). The only substrate material allowed is high-resistivity silicon. The only dielectrics are SiO2 (thermal and PECVD) and Si3N4 (PECVD). The only metal allowed is AlSi (1%) by sputtering.
>> The wafers have the backside almost completed (metal already patterned - need only overglass) and the frontside at metal1: that is, I have to deposit a dielectric, open the vias, deposit and pattern the second metal and put the overglass. I have already identified and took most of the trainings on the tools I plan to use for this process.
>> I believe that the whole process is entirely CMOS compatible and the wafers do not present any harm to the SNF community.
>> Please let me know if I can proceed or if you need more info.
> Mary X. Tang, Ph.D.
> Stanford Nanofabrication Facility
> Paul G. Allen Room 136, Mail Code 4070
> Stanford, CA 94305
> mtang at stanford.edu
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