From rik at snf.stanford.edu Wed Oct 14 23:22:27 2009 From: rik at snf.stanford.edu (rik at snf.stanford.edu) Date: Wed, 14 Oct 2009 23:22:27 -0700 Subject: Comment sts SNF 2009-10-14 23:22:26: Started clean @ 9 pm Message-ID: Started Etchback3 From faridz at snf.stanford.edu Tue Oct 20 16:50:02 2009 From: faridz at snf.stanford.edu (faridz at snf.stanford.edu) Date: Tue, 20 Oct 2009 16:50:02 -0700 Subject: Problem sts SNF 2009-10-20 16:50:02: Sio2 thickness too high Message-ID: I ran 7 wafers 3 diffrent runs 3 wafers came out without any SiO2 thickness and other four measure SiO2 thickness too high.!!! From ehe at snf.stanford.edu Tue Oct 20 21:45:39 2009 From: ehe at snf.stanford.edu (ehe at snf.stanford.edu) Date: Tue, 20 Oct 2009 21:45:39 -0700 Subject: Comment sts SNF 2009-10-20 21:45:38: 10% thickness variation from center to edge Message-ID: 350C SiO2 deposition Found chip fragments under seal, cleaned most of the chip dust out From ehe at snf.stanford.edu Wed Oct 21 11:31:32 2009 From: ehe at snf.stanford.edu (ehe at snf.stanford.edu) Date: Wed, 21 Oct 2009 11:31:32 -0700 Subject: Problem sts SNF 2009-10-21 11:31:31: needs tune-up Message-ID: something is out of whack, parameters fluctuate during deposition (more than usual) and thickness varies 10% from center to edge of platen and between runs; refl. power is nonzero, etc From jperez at snf.stanford.edu Thu Oct 22 06:39:00 2009 From: jperez at snf.stanford.edu (jperez at snf.stanford.edu) Date: Thu, 22 Oct 2009 06:39:00 -0700 Subject: Comment sts SNF 2009-10-14 23:22:26: Started clean @ 9 pm Message-ID: Thanks! From jperez at snf.stanford.edu Thu Oct 22 06:40:01 2009 From: jperez at snf.stanford.edu (jperez at snf.stanford.edu) Date: Thu, 22 Oct 2009 06:40:01 -0700 Subject: Comment sts SNF 2009-09-24 09:26:22: can't locate " Clean Cycle" yellow sign!!!! Message-ID: When I checked for the yellow sign it was in the STS drawer. From jperez at snf.stanford.edu Thu Oct 22 14:57:22 2009 From: jperez at snf.stanford.edu (jperez at snf.stanford.edu) Date: Thu, 22 Oct 2009 14:57:22 -0700 Subject: Problem sts SNF 2009-10-21 11:31:31: needs tune-up Message-ID: I didn't see the problem today when I loaded 4 test wafers. The only problem was the power range during a six minute deposit was 38 to 41 watts. Mostly 40/41 watts and occasionally drop to 38 W, but returned quickly to 40/41W. Here are the four average measurements; front TW top TW left sideTW right side TW thick avg. 2276A 2221A 2220A 2164A std dev 27.85 22.1 29.7 27.6 % range 1.66 1.57 1.89 2.14 IR 1.476 1.4756 forgot to log 1.475 From jperez at snf.stanford.edu Thu Oct 22 14:57:48 2009 From: jperez at snf.stanford.edu (jperez at snf.stanford.edu) Date: Thu, 22 Oct 2009 14:57:48 -0700 Subject: Comment sts SNF 2009-10-20 21:45:38: 10% thickness variation from center to edge Message-ID: Didn't see this problem. From jperez at snf.stanford.edu Thu Oct 22 14:58:30 2009 From: jperez at snf.stanford.edu (jperez at snf.stanford.edu) Date: Thu, 22 Oct 2009 14:58:30 -0700 Subject: Problem sts SNF 2009-10-20 16:50:02: Sio2 thickness too high Message-ID: I ran one pass, four wafers. All OK! From ehe at snf.stanford.edu Thu Oct 22 21:58:58 2009 From: ehe at snf.stanford.edu (ehe at snf.stanford.edu) Date: Thu, 22 Oct 2009 21:58:58 -0700 Subject: Problem sts SNF 2009-10-22 21:58:57: same as before Message-ID: I am measuring oxide thickness from center of platen to edge, not center of wafer to edge of same wafer. When the PECVD is in good working shape, the thickness stays within 3%; last time it slipped up to 10% it was because the shower spacer was coming lose. From jperez at snf.stanford.edu Thu Oct 29 07:12:04 2009 From: jperez at snf.stanford.edu (jperez at snf.stanford.edu) Date: Thu, 29 Oct 2009 07:12:04 -0700 Subject: Problem sts SNF 2009-10-22 21:58:57: same as before Message-ID: No one seems to see this problem User to see me on how to User is loading wafers on Platen.