May PEUG Mtg -- MEMS Related Plasma Etching

Jim McVittie mcvittie at cis.Stanford.EDU
Wed Apr 25 10:03:02 PDT 2001

STS Users,

On the afternoon of May 10 there will be three talks on deep Si etching.
	Jim McVittie
******************* PLASMA ETCH USERS GROUP *********************
of the Northern California Chapter of the American Vacuum Society

May 2001 MEETING

Topic:  MEMS Related Plasma Etching

Date:   Thursday, May 10, 2001
Time:   2:00 - 5:00 pm
Place:  National Semiconductor Credit Union Auditorium
             955 Kifer Rd.
             Santa Clara, CA 95051

Directions to the National Semiconductor Credit Union Auditorium:
>From 101: Go south on Lawrence Expressway. Turn right on Kifer Rd. 
Turn right into the driveway of the National Semiconductor Credit Union (955
Kifer Rd.) and find parking in the Credit Union parking lot. The auditorium
is on the west side of the building and can be entered from the door in the
rear next to the company park.

>From 280: Go north on Lawrence Expressway. Turn left on Kifer Rd. 
Follow directions above.

See a map:

Agenda: 2:00 - 2:30 Refreshments
         2:30 - 4:00 Presentations

Chair: Jim McVittie, mcvittie at cis.Stanford.EDU


Deep Reactive Ion Etching (DRIE) for Multi-Wafer Projects

Arturo Ayon
Sony Semiconductor
1 Sony Place
San Antonio, TX 78245-2100

We review the physics and the performance of a DRIE tool, the influence of
etching variables on anisotropy, uniformity, silicon etching rate,
selectivity and scalloping. We discuss the charging effects observed on
high aspect ratio structures when employing SOI substrates, the dependance
of the footing effect on etching conditions, and the utilization of the
local electric fields generated when reaching a dielectric stop layer for
achieving ion flux steering.

The utilization of deep reactive ion etching (DRIE) in conjunction with
wafer bonding schemes makes possible the micromanufacturing of complex
3-dimensional structures at a microscale level, in a manner not previously
practical and in some cases unattainable. Plasma etching methods, in
general, limit the geometry to extruded 2D prismatic shapes. However, DRIE
in combination with wafer bonding techniques offers to designers the
flexibility not available to the previous generation of technologists.

These techniques have been successfully applied in the microfabrication of a
large variety of structures including bipropellant silicon
micro-rockets, heat exchangers, turbo chargers and micro-combustors.

Low Frequency Deep Reactive Ion Etching for SOI Processing

Matthew Wasilik
Berkeley Sensor & Actuator Center
497 Cory Hall
Berkeley, CA 94720-1770

Due to the inherently non-uniform etching effects in the standard DRIE
process, a new technique has been developed specifically for SOI (Silicon
On Insulator) etching.In short, a separate pulsed, low frequency power
input is applied to the platen during the etching cycle. This essentially
allows ions to escape more readily from deep trenches when the etching
cycle is done. From this a decrease in over-etch sensitivity emerges, and
the notching or ^footing^ of Silicon structures is minimized. The end
result is the ability to produce high quality large aspect ratio

Advanced Deep Silicon Etching for Deep Trench Isolation, Optical
and Micro-Machining Applications

Padmapani Nallan, Anisul Khan, Sharma Pamarthy, Shu-Ting Hsu, Ajay Kumar

Applied Materials
3320 Scott Boulevard
Santa Clara, CA 95054

Traditionally, deep silicon etching has been used for DRAM capacitor
trenches and deep trench isolation applications for BiCMOS devices.
Recently, we have seen a plethora of new applications requiring deep
silicon etching (thru wafer etches for inkjet applications and optical
fiber alignment, microsensors and actuators etc.). The etch requirements
for all these applications are as diverse as the applications themselves.
The CDs range from sub-micon to millimeter sizes and the etch depths range
from a 1-2um to through wafer (~700um for a six inch wafer).  Some
applications such as waveguides require very smooth sidewall (typical
requirement is <4nm surface roughness to avoid light scattering), while
through wafer etches require very high etch rates (>10um/min) with very
high selectivity to resist and hardmask (typically >70:1). These varied
applications with a wide range of etch requirements have motivated us to
develop a portfolio of processes, in the DPS-DT chamber, which cater to
different application needs. We have used two different approaches to
develop processes that satisfy the requirements of the different
applications. One is a single step approach where we use a SF6/HBr/O-2 or
a SF6/C4F8 chemistry to etch the trenches. This approach is necessary for
applications where smooth sidewalls are required. An SF6 based etch
chemistry was chosen to get high etch rates.  The other is the Time
Multiplex Gas Modulation (TMGM)  approach, where we have a sequence of
short deposition and etch steps cycled many times over to get the required
etch depth. This approach gives a high etch rate with very high
selectivity to both oxide and resist.  The capabilities of our tool with
all these processes will be presented.


Della Miller
AVS West
1265 El Camino Real, Ste. 109
Santa Clara CA 95050

Phone:   408-246-3600
Fax:       408-246-7700
E-mail:   della at

More information about the sts mailing list