thin insulating SiN films
afflannery at attbi.com
Tue Dec 3 10:20:26 PST 2002
It's not an absolute thing. There's a yield curve vs. thickness that has a
knee somewhere. Where that knee is is soooo dependent on
1. Chamber condition prior to dep
2. Cleanliness of wafers and handling
3. Voltage requirements
4. Recipe used
5. Post dep processing.
6. Substrate material
7. Surface area of the device (there is definitely a defect density so you'd
have to work it out statistically).
I'll also point out based on your subsequent e-mail that using 10 nm of Pt
alone to mask your nitride in the MRC means that you also have to be
concerned about the additional effects of pinholes in your mask. Photoresist
would make that less of an issue. Also not sure why you don't etch it in
drytek1. Less of an issue with sputter etching, hence selectivity.
That't the long answer. The short answer is you're probably o.k. with a
reasonable yield for 100 nm at moderate voltates if the wafers and chamber
are clean and you don't subject the nitride to anything taxing. Quick to
----- Original Message -----
From: "Yves Acremann" <acremann at SLAC.Stanford.EDU>
To: <sts at snf.stanford.edu>
Sent: Monday, December 02, 2002 4:44 PM
Subject: thin insulating SiN films
> We need to make thin insulating layers of SiN on GaAs ? AlPt. What is
> the minimal thickness at which
> the SiN film (made with STS) is reliabely (no piholes) insulating? Are
> 10nm realistic / can we go thinner?
More information about the sts