Pits in PECVD oxide on Au
alexneu at stanford.edu
Tue May 4 18:59:08 PDT 2010
I haven't figured out precisely what caused my problem but I have found a
work-around. Thank you to the several users who who offered advice over the
past few days.
Several people suggested possible problems with the temperature of the
machine and my choice of metals. I put a blank silicon chip with Ti/Au on it
in the tool, pumped down, waited for a half hour and then inspected it -
there was no change. At the process clinic on Monday I learned that
evaporated gold doesn't form a pinhole-free coat until it's about 30 nm
thick, meaning my 25 nm thick layer may have had pinholes through to the Ti
Ed Myers reported previous success using the STS to isolate chrome/gold so I
switched to chrome/gold and was able to put down pinhole-free oxide and
nitride. I kept the gold layer 25 nm thick. The chrome adhesion layer ended
up being ~300nm due to a crystal monitor malfunction. I used the 100 nm
standard nitride recipe and my 50 nm standard oxide recipe, running the
nitride chip first. For each deposition I did a dry run on the machine
before running the process on the test chip. Using an interferometer I
measured the dielectric thicknesses as 89 nm and 50 nm respectively.
I tested for pinholes by evaporating gold cross-bars on top of the coated
Cr/Au strips and in both cases found no shorting, indicating no leaks over
an area 100 um wide and a few mm long.
Using an AFM and optical inspection I found lots of micron-sized
particulates on the SiO2 sample. The nitride sample had far fewer particles.
I didn't see the previously reported pitting on either sample.
If anyone would like more details on my process please let me know.
On Fri, Apr 30, 2010 at 1:31 PM, Alex Neuhausen <alexneu at stanford.edu>wrote:
> Hi STS users,
> I'm trying to put a 50 nm PECVD oxide on top of Ti/Au traces (5/25 nm). The
> oxide on top of bare wafer is fine, but the area on top of the Au is covered
> with pits, as confirmed with AFM and optical microscope. The pits are
> roughly 0.5 um diameter and spaced every few um. I've reduced my process to
> simply cleaning a chip, evaporating unpatterned metal, an oxygen plasma RIE
> to clean any organics, and immediate transfer to the STS and I still see
> pitting. Because the pits are localized to the Au and I've tried to
> eliminate any contamination, I have a theory that this is caused by thermal
> stress between the Ti/Au and surrounding oxide. Is anyone else using the STS
> to put oxide on top of gold and have you had any problems?
> Alex Neuhausen
> PhD Candidate Electrical Engineering
> Goldhaber-Gordon Lab
> 476 Lomita Mall
> Stanford, CA 94305
> Office: 650-725-2047
> Cell: 650-776-5672
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