From axiu at snf.stanford.edu  Fri Nov  3 11:24:48 2006
From: axiu at snf.stanford.edu (axiu at snf.stanford.edu)
Date: Fri, 3 Nov 2006 11:24:48 -0800
Subject: Problem stsetch SNF 2006-11-03 11:24:47: no plasma, no etching with/without holder
Message-ID: <mailman.1278.1357938652.25867.stsetch-pcs@snf.stanford.edu>




From cbaxter at snf.stanford.edu  Fri Nov  3 12:41:27 2006
From: cbaxter at snf.stanford.edu (cbaxter at snf.stanford.edu)
Date: Fri, 3 Nov 2006 12:41:27 -0800
Subject: Problem stsetch SNF 2006-11-03 11:24:47: no plasma, no etching with/without holder
Message-ID: <mailman.1279.1357938652.25867.stsetch-pcs@snf.stanford.edu>

Run o2 clean and adjusted b/s he tolerrance setting.



From praveen at snf.stanford.edu  Thu Nov 16 17:34:22 2006
From: praveen at snf.stanford.edu (praveen at snf.stanford.edu)
Date: Thu, 16 Nov 2006 17:34:22 -0800
Subject: Problem stsetch SNF 2006-11-16 17:34:22: No RF plasma
Message-ID: <mailman.1280.1357938652.25867.stsetch-pcs@snf.stanford.edu>

Gave coil error and no RF plasma. Was able to abort and unload the wafer.



From ericp at snf.stanford.edu  Thu Nov 16 18:48:20 2006
From: ericp at snf.stanford.edu (ericp at snf.stanford.edu)
Date: Thu, 16 Nov 2006 18:48:20 -0800
Subject: Comment stsetch SNF 2006-11-16 18:48:19: tests ok
Message-ID: <mailman.1281.1357938652.25867.stsetch-pcs@snf.stanford.edu>

I loaded a dummy, and it etches fine.  
I can only guess that the prev. problem was due 
to a backside He high leakrate. 
The only thing I notice is that the wafer is loading 
a little off-center, which could contribute to a He flow 
problem.  



From eenriquez at snf.stanford.edu  Fri Nov 17 07:15:06 2006
From: eenriquez at snf.stanford.edu (eenriquez at snf.stanford.edu)
Date: Fri, 17 Nov 2006 07:15:06 -0800
Subject: Problem stsetch SNF 2006-11-16 17:34:22: No RF plasma
Message-ID: <mailman.1282.1357938652.25867.stsetch-pcs@snf.stanford.edu>

See previous comment



From kattsai at snf.stanford.edu  Fri Nov 17 13:55:39 2006
From: kattsai at snf.stanford.edu (kattsai at snf.stanford.edu)
Date: Fri, 17 Nov 2006 13:55:39 -0800
Subject: Comment stsetch SNF 2006-11-17 13:55:38: coil power out of tolerance message
Message-ID: <mailman.1283.1357938652.25867.stsetch-pcs@snf.stanford.edu>

kept getting coil power out of tolerance message. substrates did not etch.



From latta at snf.stanford.edu  Tue Nov 28 13:07:25 2006
From: latta at snf.stanford.edu (latta at snf.stanford.edu)
Date: Tue, 28 Nov 2006 13:07:25 -0800
Subject: Comment stsetch SNF 2006-11-17 13:55:38: coil power out of tolerance message
Message-ID: <mailman.1284.1357938652.25867.stsetch-pcs@snf.stanford.edu>

This is due to the He leak rate being too high.  Yes, I know that it doesn't say that, but if the He leak is too high the plasma will not strike.
Usually this is due to the wafer.  Either it has punched through in an area or there is something on the back oif the substrate causing a leaky seal with the chuck.
Please see Elmer's comment of 10 Oct 2006.



From latta at snf.stanford.edu  Tue Nov 28 13:08:29 2006
From: latta at snf.stanford.edu (latta at snf.stanford.edu)
Date: Tue, 28 Nov 2006 13:08:29 -0800
Subject: Comment stsetch SNF 2006-11-16 18:48:19: tests ok
Message-ID: <mailman.1285.1357938652.25867.stsetch-pcs@snf.stanford.edu>

Noted.  Uncenteredness will be addressed during the Winter Shutdown pm.