From cbaxter at snf.stanford.edu  Wed May  5 23:14:50 2004
From: cbaxter at snf.stanford.edu (Cesar Baxter)
Date: Wed, 05 May 2004 23:14:50 -0700
Subject: STSETCH
Message-ID: <4099D7DA.490F7AFC@snf.stanford.edu>


To ALL User,

  The phase/mag detector on rf coil arc internally, this is probably
due to over loading when the air cap failed last week. Elmer will
check with STS local rep or other vendor for part availability. The
tool will remain on shutdown until repair are complete.


Cesar


From izuleta at stanford.edu  Wed May  5 23:09:56 2004
From: izuleta at stanford.edu (Ignacio A. Zuleta)
Date: Wed,  5 May 2004 23:09:56 -0700
Subject: rookie questions
Message-ID: <1083823796.4099d6b445101@webmail.stanford.edu>

Dear STS users,

I am in the process of optimizing a process flow that involves the use of 
the STS machine here in the lab. I am considering using oxide as a mask, 
and I wanted to check that I am thinking about the process right. I am 
planning to use tylanbpsg to put oxide on a Al-coated double-polished 
wafer(just one side), then I planned to pattern the oxide (and the Al 
layer) with the same mask using the P5000, finally STSetching trenches and 
release windows on the front and back of my wafer, respectively. The 
questions I have are:

* Is the P5000 plasma etcher the right tool to pattern the oxide?

* Are oxide masks better in any sense than PR masks in an STS etch?

Thanks,

Ignacio
-- 
Ignacio A. Zuleta
Chemistry Department
Stanford University
Office: (650)723-4332
Cellphone: (650)799-9225
Fax: (650)725-0259


From mbartsch at stanford.edu  Thu May  6 00:53:13 2004
From: mbartsch at stanford.edu (Michael S. Bartsch)
Date: Thu, 6 May 2004 00:53:13 -0700 (PDT)
Subject: rookie questions
In-Reply-To: <1083823796.4099d6b445101@webmail.stanford.edu> from "Ignacio A. Zuleta" at May 05, 2004 11:09:56 PM
Message-ID: <200405060753.i467rD61002125@elaine43.Stanford.EDU>

Hello Ignacio,

I can't speak to the use of the P5000, but my understanding is that the
STS requires a photoresist mask in order to achieve its high aspect ratio
etches.  Basically your PR mask is what provides the etcher with the
polymer components it needs to passivate the etched side-walls as the
machine cycles through etch and passivation steps.  With an oxide mask
only and no source of polymer, I don't believe you can get the nice,
vertical side-walls you probably want from the etch.

Good luck,
Mike


> 
> Dear STS users,
> 
> I am in the process of optimizing a process flow that involves the use of 
> the STS machine here in the lab. I am considering using oxide as a mask, 
> and I wanted to check that I am thinking about the process right. I am 
> planning to use tylanbpsg to put oxide on a Al-coated double-polished 
> wafer(just one side), then I planned to pattern the oxide (and the Al 
> layer) with the same mask using the P5000, finally STSetching trenches and 
> release windows on the front and back of my wafer, respectively. The 
> questions I have are:
> 
> * Is the P5000 plasma etcher the right tool to pattern the oxide?
> 
> * Are oxide masks better in any sense than PR masks in an STS etch?
> 
> Thanks,
> 
> Ignacio
> -- 
> Ignacio A. Zuleta
> Chemistry Department
> Stanford University
> Office: (650)723-4332
> Cellphone: (650)799-9225
> Fax: (650)725-0259
> 



From bchui at california.com  Thu May  6 01:32:36 2004
From: bchui at california.com (Benjamin Chui)
Date: Thu, 06 May 2004 01:32:36 -0700
Subject: rookie questions
In-Reply-To: <200405060753.i467rD61002125@elaine43.Stanford.EDU>
Message-ID: <web-69701140@california.com>

Ignacio,

Also make sure the aluminum the way you're using it on the
wafer is allowed in the STS (it sounds like it's not
exposed, so it should be ok).

Ben


On Thu, 6 May 2004 00:53:13 -0700 (PDT)
 "Michael S. Bartsch" <mbartsch at stanford.edu> wrote:
> Hello Ignacio,
> 
> I can't speak to the use of the P5000, but my
> understanding is that the
> STS requires a photoresist mask in order to achieve its
> high aspect ratio
> etches.  Basically your PR mask is what provides the
> etcher with the
> polymer components it needs to passivate the etched
> side-walls as the
> machine cycles through etch and passivation steps.  With
> an oxide mask
> only and no source of polymer, I don't believe you can
> get the nice,
> vertical side-walls you probably want from the etch.
> 
> Good luck,
> Mike
> 
> 
> > 
> > Dear STS users,
> > 
> > I am in the process of optimizing a process flow that
> involves the use of 
> > the STS machine here in the lab. I am considering using
> oxide as a mask, 
> > and I wanted to check that I am thinking about the
> process right. I am 
> > planning to use tylanbpsg to put oxide on a Al-coated
> double-polished 
> > wafer(just one side), then I planned to pattern the
> oxide (and the Al 
> > layer) with the same mask using the P5000, finally
> STSetching trenches and 
> > release windows on the front and back of my wafer,
> respectively. The 
> > questions I have are:
> > 
> > * Is the P5000 plasma etcher the right tool to pattern
> the oxide?
> > 
> > * Are oxide masks better in any sense than PR masks in
> an STS etch?
> > 
> > Thanks,
> > 
> > Ignacio
> > -- 
> > Ignacio A. Zuleta
> > Chemistry Department
> > Stanford University
> > Office: (650)723-4332
> > Cellphone: (650)799-9225
> > Fax: (650)725-0259
> > 
> 



From han-jun.kim at hp.com  Thu May  6 11:55:55 2004
From: han-jun.kim at hp.com (Kim, Han-jun)
Date: Thu, 6 May 2004 11:55:55 -0700 
Subject: rookie questions
Message-ID: <40700B4C02ABD5119F0000902787664406C01909@hplex1.hpl.hp.com>


* Is the P5000 plasma etcher the right tool to pattern the oxide?
--> Yes!

* Are oxide masks better in any sense than PR masks in an STS etch?
--> Sure! But, PR also works as great in STS w/ descum.

Good luck!

cheers,
Han-Jun

=============================
 Han-Jun Kim                  
 Hewlett-Packard Lab.
 1501 Page Mill Rd, MS 1198
 Palo Alto, CA 94304
 (650) 857-8525 / 8948 FAX        
 hjkim at hpl.hp.com          
=============================






From mcvittie at snf.stanford.edu  Thu May  6 13:48:11 2004
From: mcvittie at snf.stanford.edu (Jim McVittie)
Date: Thu, 06 May 2004 13:48:11 -0700
Subject: rookie questions
References: <1083823796.4099d6b445101@webmail.stanford.edu>
Message-ID: <409AA48B.9A47CA8B@snf.stanford.edu>

Ignacio,

Switching from a resist mask to a oxide mask would likely affect the etch
process. Plasma etch processes are tuned to particular wafer and chamber wall
surfaces. Changing a surface material usually affects the spieces mix in the
gas phase about the wafer and thus affects the etch results. If you want to
put the time into it, you can probably develop a process to work with a oxide
mask. I would look at some of the papers published on the Bosch process to see
if someone has already done the work to tune the process for an oxide mask. I
can cantact STS and see what they recommand. As is, the present process may
give acceptable results for your needs. I expect
users have oxide mask results.

Regarding the P-5000, etching the oxide and then etching the Al should work.
The advantage of
using the P-5000 ox etch over the AMTetcher is that the P-5000 is near 10X
fast (single wafer) and the end point detect is functioning. In addition, it
gives a steeper profile. The downside is that the selective to Si is worst.
Note that AMTetcher actually has two endpoint detectors (laser and optical
emission). The last time, I checked niether one was setup properly. If needed,
I can set them up.
                Jim McVittie

"Ignacio A. Zuleta" wrote:

> Dear STS users,
>
> I am in the process of optimizing a process flow that involves the use of
> the STS machine here in the lab. I am considering using oxide as a mask,
> and I wanted to check that I am thinking about the process right. I am
> planning to use tylanbpsg to put oxide on a Al-coated double-polished
> wafer(just one side), then I planned to pattern the oxide (and the Al
> layer) with the same mask using the P5000, finally STSetching trenches and
> release windows on the front and back of my wafer, respectively. The
> questions I have are:
>
> * Is the P5000 plasma etcher the right tool to pattern the oxide?
>
> * Are oxide masks better in any sense than PR masks in an STS etch?
>
> Thanks,
>
> Ignacio
> --
> Ignacio A. Zuleta
> Chemistry Department
> Stanford University
> Office: (650)723-4332
> Cellphone: (650)799-9225
> Fax: (650)725-0259
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From mcvittie at cis.Stanford.EDU  Thu May 13 23:59:32 2004
From: mcvittie at cis.Stanford.EDU (Jim McVittie)
Date: Thu, 13 May 2004 23:59:32 -0700 (PDT)
Subject: STS-2 Status
Message-ID: <Pine.LNX.4.44.0405132353440.21015-100000@cis.Stanford.EDU>

STS Users,

The installation of the new STS etcher is finally finished and the
hardware phase of the startup in complete. We have started the process
characterization.  The startup is running a bit late because of some
problems with the loader, which pushed the process startup into conflict
with vacation plans for the STS process expert. For this reason, the
process expert will not be getting here until the 26th or 27th of this
month.  In the mean time, the STS hardware engineer (Duncan Drysdale)is
helping us startup the process and is training our staff.  It is now
looking like we will start the training of the present STS users on the
new tool during the second week in June. Between now and then, we will be
characterizing the tool for a variety of patterns and etch depths, and
preparing training material.

The processes on the new tool are significantly different than those used 
on the old tool. There are a number a new parameters, which give the tool 
more capability, but they also make process selection more complicated. My 
goal is to have 5 or 6 characterized processes to choose from when you 
switch over to the new tool. Once we have everyone switched to the new 
tool, it looks like we will be opening up the old tool to wafer with gold 
and other metals. If gold is no problem to your devices, you can elect to 
stay with the old tool. 

The initial process work is going well. We have pretty much duplicated the
pre-shipment tests done in England. These includes a 25um deep 2 um wide
trench and a 300 um deep 50um wide trench. We have already started making
a training video. An initial version of this video will be used to train
the staff and some super users starting Monday. Some of the
patterns/structures that we will be working on as of next week include:
SOI, High Aspect Ratio Structures, Though Wafer Etch, High Exposed Areas,
Pillar Structures and Smooth walls.  STS has supplied us with starting
processes for these pattern/structures. The plan is to have initial
results for all these cases when the STS process expert shows up.  With
his help we will quickly tune up the processes and open up the tool to
general use.

	Thanks, Jim
 
--------------------------------------------------------------
Jim McVittie, Ph.D.    			Senior Research Scientist 
Allen Center for Integrated Systems     Electrical Engineering
Stanford University             	jmcvittie at stanford.edu
Rm. 336, 330 Serra Mall			Fax: (650) 723-4659
Stanford, CA 94305-4075			Tel: (650) 725-3640




From kenney at slac.stanford.edu  Mon May 17 17:24:04 2004
From: kenney at slac.stanford.edu (Chris Kenney)
Date: Mon, 17 May 2004 17:24:04 -0700 (PDT)
Subject: Monday time available
Message-ID: <Pine.GSO.4.58.0405171721470.11745@flora05.slac.stanford.edu>

My etch should finish around 8:30 PM tonight.

The reservation under Latta from about 830PM through
midnight will be available.

Chris


From tkramer at stanford.edu  Sat May 22 17:44:59 2004
From: tkramer at stanford.edu (Theresa Anne Kramer)
Date: Sat, 22 May 2004 17:44:59 -0700
Subject: stsetch available 5/22/04: now to 20:00
Message-ID: <1085273099.40aff40b17d2c@webmail.stanford.edu>



finished early and the next hour is unreserved


From mbartsch at stanford.edu  Sat May 22 22:42:22 2004
From: mbartsch at stanford.edu (Michael S. Bartsch)
Date: Sat, 22 May 2004 22:42:22 -0700 (PDT)
Subject: Res removed Sunday 8am-noon
Message-ID: <200405230542.i4N5gMtD010714@elaine15.Stanford.EDU>



From latta at snf.stanford.edu  Tue May 25 11:05:07 2004
From: latta at snf.stanford.edu (Nancy Latta)
Date: Tue, 25 May 2004 11:05:07 -0700
Subject: Etcher available until 1:00 today
Message-ID: <40B38AD3.4040002@snf.stanford.edu>




From vossough at snf.stanford.edu  Tue May 25 20:12:46 2004
From: vossough at snf.stanford.edu (Kris Vossough)
Date: Tue, 25 May 2004 20:12:46 -0700 (PDT)
Subject: DRIE free from now - 21:00
Message-ID: <Pine.LNX.4.04.10405252011220.9985-100000@snf.stanford.edu>







From mbartsch at stanford.edu  Thu May 27 21:27:07 2004
From: mbartsch at stanford.edu (Michael S. Bartsch)
Date: Thu, 27 May 2004 21:27:07 -0700 (PDT)
Subject: STS free Friday 5-7pm
Message-ID: <200405280427.i4S4R7I4027061@elaine15.Stanford.EDU>



From Spotworthy at aol.com  Fri May 28 08:50:03 2004
From: Spotworthy at aol.com (Spotworthy at aol.com)
Date: Fri, 28 May 2004 11:50:03 -0400
Subject: STS etch available today 9:30-1:00
Message-ID: <7AB36055.48863F52.0CEC25E7@aol.com>

I have also removed my reservations for sat morning, monday morning and tuesday morning.
Wafers won't be ready.

Linda W.


From eap at gloworm.Stanford.EDU  Fri May 28 16:32:02 2004
From: eap at gloworm.Stanford.EDU (Eric Perozziello)
Date: Fri, 28 May 2004 16:32:02 -0700 (PDT)
Subject: STS time tonight
Message-ID: <Pine.GSO.4.44.0405281630001.25187-100000@gloworm.Stanford.EDU>


Hi All,

Unfortunately, the masks were supposed to be delivered today weren't, so
the time that Mike Bartsch had given to me tonight is up for grabs.

Sorry for the late notice...

-Eric