question on STSETCH recipe to minimize trench widening
xzhuang at stanford.edu
Wed Oct 12 11:42:11 PDT 2005
Dear STSETCH users,
I have a question regarding the recipe to use for etching straight trenches.
I am trying to etch 10 um wide trenches on a 120 um thick silicon substrate.
The etching will be terminated by an oxide layer. I used the standard
"deep" recipe and had a problem with the trench widening during etching.
At 100um deep, the trenches are widened by about 5um. It is especially bad
at the end of the trench where sideway etching is very pronounced (trenches
are widened by more than 10 um). For my process, it is critical that the
trenches remain <15um wide. I understand the sideway etching at the
silicon/oxide interface is partly due to over etching. But how about the
widening during the etching? Is that another recipe that mitigates this
problem? Any input will be highly appreciated!
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