PlasmaTherm DRIE Discussion Minutes 11/14/12
edmyers at stanford.edu
Wed Nov 14 14:03:21 PST 2012
Here are my notes from today's DRIE discussion. Please let me know if I
As mentioned during the meeting, the items brought up fall in to two
categories. One category relates to policy and the other relates to
capability. These are not rank ordered, but are listed in roughly the
order they were presented.
1) Gold Contaminated DRIE capability
2) Use of metal hard masks
3) Clearer policy on the use of Crystalbond
4) Ge DRIE etch policy
5) Use of the wafer carrier and protection ring in STSetch2 and PT-DSE
1) High Aspect / Deep Via: 2-20um through wafer etches
2) Verticle Sidewalls: Seeing 70-80 degree slopes on STSetch when
etching through a handle wafer
3) No SOI footing: Seeing problems with SOI footing on STSetch
4) No Grassing: Seeing more frequent and random grassing on STSetch
5) No CD expansion: 20um holes become 26um holes during a through wafer
6) Reliable sidewall slops: Seeing a lot of variation in profile angles
with time (STSetch)
7) Smooth sidewalls: Scalloping of less than 10nm for 100um deep etches
8) Better resist selectivity: Seeing poor selectivity on STSetch2
1) Ed to post the acceptance reports on the wiki
2) Interested lab members to contact Ed to volunteer for recipe development.
1) All the new etch systems are available to lab members willing to help
develop etch recipes, with the following caveats:
A) The recipe development objective must be pre-approved by Ed.
B) All results must be shared, by posting on the lab member's wiki.
C) No more than 3 runs will be allowed, unless there are published results.
D) The Oxford III-V must complete acceptance before it becomes available
to lab members for recipe development.
E) The correct Operator/Engineer/Maintenance levels and passwords must
be established on the tool.
More information about the stsetch