From ahazeghi at stanford.edu Thu Sep 2 20:00:21 2010 From: ahazeghi at stanford.edu (Arash Hazeghi) Date: Thu, 2 Sep 2010 20:00:21 -0700 (PDT) Subject: Please do not change stnadard track program Message-ID: <519284592.481849.1283482821107.JavaMail.root@zm03.stanford.edu> I noticed program #4 on track 2 had been modified, please do NOT change the program and then leave it without notice, you might ruin other users' process. I changed the parameters back to default. Thanks, Arash -------------- next part -------------- An HTML attachment was scrubbed... URL: From mahnaz at stanford.edu Fri Sep 3 08:21:26 2010 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 03 Sep 2010 08:21:26 -0700 Subject: Program 8 Message-ID: <4C811276.103@stanford.edu> Hello all, I see many emails and complains about some one changing recipes on standard programs. First of all, you are not allowed to change. But as much as I like to take program 8 for creating a new recipe, I have left it intentionally for users whom like to change/modify a recipe. And there is a recipe loaded in program 8 all you have to do change the time and you will have your recipe. When you do change a recipe please be courteous and put it back for the next innocent soil. mahnaz From ahazeghi at stanford.edu Tue Sep 28 23:01:02 2010 From: ahazeghi at stanford.edu (Arash Hazeghi) Date: Tue, 28 Sep 2010 23:01:02 -0700 Subject: Bake problem with SVGDEV track 2 Message-ID: <05ea01cb5f9b$b27fca40$177f5ec0$@edu> Hi, In the past three weeks I have had issues with my lift off process, after calibrating exposure and focus with ASML many times, I still had inconsistent results, the outer dies on the wafer showed artifacts after liftoff. My devices have min CD (0.5um) lines and spaces, this happened for both 1um and 1.6um 3612 PR. The inner dies were perfect at the same time. A few times I could see a circular trace on the wafer with the center of the wafer looking a bit brighter than the edges. Mahnaz suggested that this was a result of underexposure for the outer dies. However after consulting with ASML engineers and carefully inspecting leveling for each die it was determined that all dies are exposed consistently. Last night I noticed a wafer showing the same circular trace when it went through post exposure bake on SVGDEV track #2 (front). Since the wafer had not been developed, only the track hot plate could have caused this visually-apparent artifact . Today I checked temperature uniformity for track 2 hot plate with an IR sensor, to my surprise it seems that the hot plate is not even sitting at 110C but it is about 50C and only when you hit "start" it is warmed up to the bake temperature. The hot plate on track 2 seems to be sitting at ~120C all the time. There is also a huge temperature gradient on this track with top side as high as 120C and the lower and right side falling to about 40C, here you can see how the temperature changes as I move the laser spot around the wafer. http://www.youtube.com/watch?v=6Yk3PukBYlg This is very problematic for people who want to resolve near min CD features across a whole wafer. Perhaps it is better to devote a separate hot plate with a clean and even surface for post exposure bake which the users will not use for braining samples that have resist/contamination on the bask side. Thanks, Arash ---------------------------------------------------------------------------- ------ Arash Hazeghi PhD Candidate Stanford Center for Integrated Systems CIS-X 300, 420 Via Palou Mall, Stanford, CA 94305 phone: +1-650-725-0418 web: http://www.stanford.edu/~ahazeghi -------------- next part -------------- An HTML attachment was scrubbed... URL: From gsosa at stanford.edu Wed Sep 29 15:38:48 2010 From: gsosa at stanford.edu (Gary J Sosa) Date: Wed, 29 Sep 2010 15:38:48 -0700 (PDT) Subject: Bake problem with SVGDEV track 2 In-Reply-To: <5168D2F6EE2EFA4E8382E57091B4DCDE0474C5ADE0@USWILX884.sn-us.asml.com> Message-ID: <591291307.858627.1285799928073.JavaMail.root@zm08.stanford.edu> Hi Arash... I measured the hotplate temperature on both developer tracks with our test instruments. Everything looks good. I also made sure that the hotplate vacuum was working properly and that wafers were held in firm contact to the hotplate surface. Here are the results of the measurements: Target temperature set at 110 Deg. C. Measured Temperature- Developer #2(Front): 110.2 Deg C. Uniformity: 0.23% Developer #1(Back): 109.9 Deg C. Uniformity: 0.23% Used a thermocouple wafer to measure the target temperature at the center of the hotplate. Used a surface contact thermometer to measure the hotplate uniformity . Both hotplates are within <.5 degrees of setpoint and within .3 degrees of each-other. ... Gary ----- Original Message ----- From: "Linda Ohara" To: "Gary J Sosa" Sent: Wednesday, September 29, 2010 10:31:56 AM Subject: FW: Bake problem with SVGDEV track 2 ? From: Arash Hazeghi [mailto:ahazeghi at stanford.edu] Sent: Tuesday, September 28, 2010 11:01 PM To: 'Mary Tang'; Mahnaz Mansourpour; 'Thumser, Uli' Cc: Ping Ding; svgdev2 at snf.stanford.edu Subject: Bake problem with SVGDEV track 2 Hi, ? In the past three weeks I have had issues with my lift off process, after calibrating exposure and focus with ASML many times, I still had inconsistent results, the outer dies on the wafer showed artifacts after liftoff. My devices have min CD (0.5um) lines and spaces, this happened for both 1um and 1.6um 3612 PR. The inner dies were perfect at the same time. A few times I could see a circular trace on the wafer with the center of the wafer looking a bit brighter than the edges. Mahnaz suggested that this was a result of underexposure for the outer dies. However after consulting with ASML engineers and carefully inspecting leveling for each die it was determined that all dies are exposed consistently. Last night I noticed a wafer showing the same circular trace when it went through post exposure bake on SVGDEV track #2 (front). Since the wafer had not been developed, only the track hot plate could have caused this visually-apparent artifact . Today I checked temperature uniformity for track 2 hot plate with an IR sensor, to my surprise it seems that the hot plate is not even sitting at 110C but it is about 50C and only when you hit ?start? it is warmed up to the bake temperature. The hot plate on track 2 seems to be sitting at ~120C all the time. There is also a huge temperature gradient on this track with top side ?as high as 120C and the lower and right side falling to about 40C, here you can see how the temperature changes as I move the laser spot around the wafer. ? http://www.youtube.com/watch?v=6Yk3PukBYlg ? This is very problematic for people who want to resolve near min CD features across a whole wafer. Perhaps it is better to devote a separate hot plate with a clean and even surface for post exposure bake which the users will not use for braining samples that have resist/contamination on the bask side. ? ? Thanks, Arash ? ---------------------------------------------------------------------------------- Arash Hazeghi ? PhD Candidate Stanford Center for Integrated Systems CIS-X 300, 420 Via Palou Mall, Stanford, CA 94305 ? phone: +1-650-725-0418 web: http://www.stanford.edu/~ahazeghi ? -- The information contained in this communication and any attachments is confidential and may be privileged, and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. Unless explicitly stated otherwise in the body of this communication or the attachment thereto (if any), the information is provided on an AS-IS basis without any express or implied warranties or liabilities. To the extent you are relying on this information, you are doing so at your own risk. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. ASML is neither liable for the proper and complete transmission of the information contained in this communication, nor for any delay in its receipt. From ahazeghi at stanford.edu Wed Sep 29 16:15:18 2010 From: ahazeghi at stanford.edu (Arash Hazeghi) Date: Wed, 29 Sep 2010 16:15:18 -0700 Subject: Bake problem with SVGDEV track 2 In-Reply-To: <591291307.858627.1285799928073.JavaMail.root@zm08.stanford.edu> References: <5168D2F6EE2EFA4E8382E57091B4DCDE0474C5ADE0@USWILX884.sn-us.asml.com> <591291307.858627.1285799928073.JavaMail.root@zm08.stanford.edu> Message-ID: <020e01cb602c$2ef86790$8ce936b0$@edu> Thanks Gary for checking, Did you also find out what the residue on my wafers I showed you and Linda this morning from the back track was? I did not process those wafers so you can examine them further if you want Thanks, Arash Arash Hazeghi PhD Candidate Paul G. Allen Center for Integrated systems, 420 Via Palou Mall, Stanford, CA 94305, USA office: +1-650-725-0418 cell: +1-650-353-1866 web: http://www.stanford.edu/~ahazeghi -----Original Message----- From: Gary J Sosa [mailto:gsosa at stanford.edu] Sent: Wednesday, September 29, 2010 3:39 PM To: Arash Hazeghi Cc: lindaohara at snf.stanford.edu; mahnaz at snf.stanford.edu; Mary Tang; svgdev2 at snf.stanford.edu; Thumser, Uli; vilanova at snf.stanford.edu Subject: Re: Bake problem with SVGDEV track 2 Hi Arash... I measured the hotplate temperature on both developer tracks with our test instruments. Everything looks good. I also made sure that the hotplate vacuum was working properly and that wafers were held in firm contact to the hotplate surface. Here are the results of the measurements: Target temperature set at 110 Deg. C. Measured Temperature- Developer #2(Front): 110.2 Deg C. Uniformity: 0.23% Developer #1(Back): 109.9 Deg C. Uniformity: 0.23% Used a thermocouple wafer to measure the target temperature at the center of the hotplate. Used a surface contact thermometer to measure the hotplate uniformity . Both hotplates are within <.5 degrees of setpoint and within .3 degrees of each-other. ... Gary ----- Original Message ----- From: "Linda Ohara" To: "Gary J Sosa" Sent: Wednesday, September 29, 2010 10:31:56 AM Subject: FW: Bake problem with SVGDEV track 2 From: Arash Hazeghi [mailto:ahazeghi at stanford.edu] Sent: Tuesday, September 28, 2010 11:01 PM To: 'Mary Tang'; Mahnaz Mansourpour; 'Thumser, Uli' Cc: Ping Ding; svgdev2 at snf.stanford.edu Subject: Bake problem with SVGDEV track 2 Hi, In the past three weeks I have had issues with my lift off process, after calibrating exposure and focus with ASML many times, I still had inconsistent results, the outer dies on the wafer showed artifacts after liftoff. My devices have min CD (0.5um) lines and spaces, this happened for both 1um and 1.6um 3612 PR. The inner dies were perfect at the same time. A few times I could see a circular trace on the wafer with the center of the wafer looking a bit brighter than the edges. Mahnaz suggested that this was a result of underexposure for the outer dies. However after consulting with ASML engineers and carefully inspecting leveling for each die it was determined that all dies are exposed consistently. Last night I noticed a wafer showing the same circular trace when it went through post exposure bake on SVGDEV track #2 (front). Since the wafer had not been developed, only the track hot plate could have caused this visually-apparent artifact . Today I checked temperature uniformity for track 2 hot plate with an IR sensor, to my surprise it seems that the hot plate is not even sitting at 110C but it is about 50C and only when you hit ?start? it is warmed up to the bake temperature. The hot plate on track 2 seems to be sitting at ~120C all the time. There is also a huge temperature gradient on this track with top side as high as 120C and the lower and right side falling to about 40C, here you can see how the temperature changes as I move the laser spot around the wafer. http://www.youtube.com/watch?v=6Yk3PukBYlg This is very problematic for people who want to resolve near min CD features across a whole wafer. Perhaps it is better to devote a separate hot plate with a clean and even surface for post exposure bake which the users will not use for braining samples that have resist/contamination on the bask side. Thanks, Arash ---------------------------------------------------------------------------------- Arash Hazeghi PhD Candidate Stanford Center for Integrated Systems CIS-X 300, 420 Via Palou Mall, Stanford, CA 94305 phone: +1-650-725-0418 web: http://www.stanford.edu/~ahazeghi -- The information contained in this communication and any attachments is confidential and may be privileged, and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. Unless explicitly stated otherwise in the body of this communication or the attachment thereto (if any), the information is provided on an AS-IS basis without any express or implied warranties or liabilities. To the extent you are relying on this information, you are doing so at your own risk. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. ASML is neither liable for the proper and complete transmission of the information contained in this communication, nor for any delay in its receipt.