Problem tel SNF 2008-08-28 17:04:24: improper load out of wafers

gth at gth at
Thu Aug 28 17:04:25 PDT 2008

This is again a problem which was intermittent before but now it is consistent
The wafer unloading into the LL (after the process finishes), is not proper. There is a gap/clearance of ~ 1 cm. This is a problem as it fails to recognize the wafers when it has to reload or when conditioning (LL1) and process (LL3) are used together as part of a macro
The workaround has been to put another wafer in LL2 position

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