From qran at stanford.edu Thu Oct 20 19:33:52 2011 From: qran at stanford.edu (Qiushi (Helen) Ran) Date: Thu, 20 Oct 2011 19:33:52 -0700 (PDT) Subject: thermcopoly1 time release from 10am to 3pm tmr Message-ID: <1489947946.1930484.1319164432204.JavaMail.root@zm04.stanford.edu> Sample is not ready. Qiushi(Helen) Ran ========================================= Department of Electrical Engineering Stanford University, Stanford, CA 94305. Mobile: +1-650-796-1439 Email: qran at stanford.edu From qran at stanford.edu Mon Oct 24 19:53:28 2011 From: qran at stanford.edu (Qiushi (Helen) Ran) Date: Mon, 24 Oct 2011 19:53:28 -0700 (PDT) Subject: questions for thermcopoly1 P620B2H6 recipe Message-ID: <1219982008.2065537.1319511208764.JavaMail.root@zm04.stanford.edu> Hi, guys, Sorry to spam all. I have a question for P620B2H6 recipe. I ran this recipe for 40min with B2H6 gas flow 10. The thickness of the polysilicon is 400nm as expected. However, I measured the resistance of the film by using Prometrix, it is around 370 ohm/sq. This result is quite different from the calibrate result on SNF's website (69 ohm/sq). Does anyone know why there is a big difference? Any comments, suggestions are welcome. Thanks, Helen Qiushi(Helen) Ran ========================================= Department of Electrical Engineering Stanford University, Stanford, CA 94305. Mobile: +1-650-796-1439 Email: qran at stanford.edu From robinhmb at yahoo.com Mon Oct 24 20:36:23 2011 From: robinhmb at yahoo.com (Robin King) Date: Mon, 24 Oct 2011 20:36:23 -0700 (PDT) Subject: questions for thermcopoly1 P620B2H6 recipe In-Reply-To: <1219982008.2065537.1319511208764.JavaMail.root@zm04.stanford.edu> References: <1219982008.2065537.1319511208764.JavaMail.root@zm04.stanford.edu> Message-ID: <1319513783.14335.YahooMailNeo@web111507.mail.gq1.yahoo.com> Hi Qiushi, Did you anneal the wafers afterward?? Best, Robin King / IBM ________________________________ From: Qiushi (Helen) Ran To: thermcopoly1 at snf.stanford.edu Sent: Monday, October 24, 2011 7:53 PM Subject: questions for thermcopoly1 P620B2H6 recipe Hi, guys, Sorry to spam all. I have a question for P620B2H6 recipe. I ran this recipe for 40min with B2H6 gas flow 10. The thickness of the polysilicon is 400nm as expected. However, I measured the resistance of the film by using Prometrix, it is around 370 ohm/sq. This result is quite different from the calibrate result on SNF's website (69 ohm/sq). Does anyone know why there is a big difference? Any comments, suggestions are welcome. Thanks, Helen Qiushi(Helen) Ran ========================================= Department of Electrical Engineering Stanford University, Stanford, CA 94305. Mobile: +1-650-796-1439 Email: qran at stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From qran at stanford.edu Wed Oct 26 22:43:06 2011 From: qran at stanford.edu (Qiushi (Helen) Ran) Date: Wed, 26 Oct 2011 22:43:06 -0700 (PDT) Subject: how to prevent growing poly-si on the backside of the wafer In-Reply-To: <1903572737.2185040.1319694004306.JavaMail.root@zm04.stanford.edu> Message-ID: <1986354013.2185104.1319694186788.JavaMail.root@zm04.stanford.edu> Hi, All sorry to spam. I have a question about how to prevent growing poly-Si on the backside of the wafer. I tried to put two wafer back-to-back in the same slot, but it didn't help. Is there some nobel-metal clamp I can use to stick two wafer together? Or Is there any bonding method to bond two wafer together, then part them after the growth? Any suggestions are welcomed. Best, Helen Qiushi(Helen) Ran ========================================= Department of Electrical Engineering Stanford University, Stanford, CA 94305. Mobile: +1-650-796-1439 Email: qran at stanford.edu From clchang6 at stanford.edu Wed Oct 26 23:09:58 2011 From: clchang6 at stanford.edu (Chienliu Chang) Date: Wed, 26 Oct 2011 23:09:58 -0700 Subject: how to prevent growing poly-si on the backside of the wafer References: <1986354013.2185104.1319694186788.JavaMail.root@zm04.stanford.edu> Message-ID: <9E3897710EE74C2190556E67FC4E8969@corp.cusa.canon.com> Dear Miss Ran, Hi, I am Chienliu. It is impossible not to deposit polysilicon on the back side. The only and easiest way is blank-etching away the backside polysilicon after deposition. There are some selective deposition method to date in the world, but they are not applicable in SNF. I think to bond any material on the back-side is unwise. It would introduce wafer cracking in the furnace. Even though it might be uncracked after deposition, it would be tightly bonded after high-temperature annealing, and then hardly separate them. Besides, no any nobel-metal clamp can tightly fix on the wafer in these high-temperature ambient. It also introduces contamination. Please discuss with me if anything I could help you. Best, Chienliu ------------------------------------------------- Chienliu Chang, Ph.D. Khuri-Yakub Laboratory Edward L. Ginzton Laboratory, Box 125 Center for Nanoscale Science & Engineering, room 101 Stanford University 348 Via Pueblo, Stanford, CA 94305-4088 Phone: 650-725-2265 Email: clchang6 at stanford.edu clchang6 at ntu.edu.tw ------------------------------------------------- ----- Original Message ----- From: "Qiushi (Helen) Ran" To: Sent: Wednesday, October 26, 2011 10:43 PM Subject: how to prevent growing poly-si on the backside of the wafer > Hi, All > sorry to spam. I have a question about how to prevent growing poly-Si on > the backside of the wafer. I tried to put two wafer back-to-back in the > same slot, but it didn't help. Is there some nobel-metal clamp I can use > to stick two wafer together? Or Is there any bonding method to bond two > wafer together, then part them after the growth? Any suggestions are > welcomed. > Best, > Helen > > Qiushi(Helen) Ran > ========================================= > Department of Electrical Engineering > Stanford University, Stanford, CA 94305. > Mobile: +1-650-796-1439 > Email: qran at stanford.edu >