From dlee76 at stanford.edu Fri Jul 8 11:12:52 2011 From: dlee76 at stanford.edu (Donkoun Lee) Date: Fri, 8 Jul 2011 11:12:52 -0700 Subject: Questions about the Si wet etching process in SOI wafer Message-ID: <620DD460-2923-4DD2-9322-AC33DFAF2D84@stanford.edu> Hi all: Recently, I used the 25% TMAH in order to wet-etch the Si layer in SOI wafer. Before etching a SOI wafer, when I used a Si wafer for the reference, the Si wafer was well etched. However, when I used the SOI wafer, the Si layer (device layer) in SOI wafer was not etched at all: The condition I used is like below: Temperature: 45 oC Concentration of TMAH: 25% The Si thickness in SOI wafer: 30 ~ 50 nm I also used the higher temperature, like ~ 70 oC. But, I could not etch the Si layer in SOI wafer. Si layer is P-type. However, the doping concentration is around 10^15/cm2. Furthermore, I double checked out the orientation of the Si layer and the orientation was (001) Could you give me a tip for solving this problem? Thank you. Kind Regards, Donkoun Lee From jimkruger at yahoo.com Fri Jul 8 12:20:59 2011 From: jimkruger at yahoo.com (jim kruger) Date: Fri, 8 Jul 2011 12:20:59 -0700 (PDT) Subject: Questions about the Si wet etching process in SOI wafer In-Reply-To: <620DD460-2923-4DD2-9322-AC33DFAF2D84@stanford.edu> Message-ID: <1310152859.83847.YahooMailClassic@web38903.mail.mud.yahoo.com> TMAH is very selective to the thin native SiO2 on all Si, much more than KOH. ?I am guessing that your SOI had a little more SiO2 than your test wafer. Use a 50:1 HF dip for 30 or 60 sec (60 sec =~ 50A) just before the TMAH, rinse but no need to dry, just into the TMAH. ?I don't think the doping plays much roll until very high levels of Boron. jim --- On Fri, 7/8/11, Donkoun Lee wrote: From: Donkoun Lee Subject: Questions about the Si wet etching process in SOI wafer To: wbgen-hpr at snf.stanford.edu Date: Friday, July 8, 2011, 11:12 AM Hi all: Recently, I used the 25% TMAH in order to wet-etch the Si layer in SOI wafer. Before etching a SOI wafer, when I used a Si wafer for the reference, the Si wafer was well etched. However, when I used the SOI wafer, the Si layer (device layer) in SOI wafer was not etched at all: The condition I used is like below: Temperature: 45 oC Concentration of TMAH: 25% The Si thickness in SOI wafer: 30 ~ 50 nm I also used the higher temperature, like ~ 70 oC. But, I could not etch the Si layer in SOI wafer. Si layer is P-type. However, the doping concentration is around 10^15/cm2. Furthermore, I double checked out the orientation of the Si layer and the orientation was (001) Could you give me a tip for solving this problem? Thank you. Kind Regards, Donkoun Lee -------------- next part -------------- An HTML attachment was scrubbed... URL: