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Epi papers/images

research papers and images
File Sidewall epitaxial piezoresistor process and characterisation for in-plane force sensing applications
A.A. Barlian, N. Harjee, B.L. Pruitt -- A selective epitaxial fabrication method to form piezoresistors on the sidewalls of microfabricated cantilevers for in-plane force sensing applications and their preliminary characterisation results is reported. The piezoresistors were made of a doped silicon epitaxial layer using a selective deposition technique by tailoring the process conditions. Silicon oxide was used as a mask, dichlorosilane (DCS) was used as a source gas in a reduced pressure environment and HCl was used to improve selectivity. The authors found that the deposition rates were dependent on the trench widths. The authors further characterised the current–voltage behaviour, noise and sensitivity of these epitaxial sidewall piezoresistors. A typical cantilever had resistance of 0.6 kV, 1/f coefficient, a ¼ 8, sensitivity of 1100 V/N (880 V/m) and resolution of 9.5 nN integrated over the band 10 Hz–10 kHz. Its sensitivity and resolution are comparable to single-crystal ion implanted piezoresistors and better than most polysilicon or diffused piezoresistors.
File Room temperature 1.6 μm electroluminescence from Ge light emitting diode on Si substrate
Szu-Lin Cheng, Jesse Lu, Gary Shambat, Hyun-Yong Yu, Krishna Saraswat, Jelena Vuckovic, and Yoshio Nishi Abstract: We report the room temperature electroluminescence (EL) at 1.6 μm of a Ge n+/p light emitting diode on a Si substrate. Unlike normal electrically pumped devices, this device shows a superlinear luminescence enhancement at high current. By comparing different n type doping concentrations, we observe that a higher concentration is required to achieve better efficiency of the device. Thermal enhancement effects observed in temperature dependent EL spectra show the capability of this device to operate at room temperature or above. These detailed studies show that Ge can be a good candidate for a Si compatible light emitting device.
File Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality
A. Nayfeh, C. O. Chui, . K. C. Saraswat and T. Yonehara -- We have studied the effect of hydrogen annealing on the surface roughness of germanium (Ge) layers grown by chemical vapor deposition on silicon using atomic force microscopy and cross-sectional high resolution scanning electron microscopy (HR-SEM). Our results indicate a strong reduction of roughness that approaches 90% at 825 °C. The smoother Ge surface allowed for the fabrication of metal-oxide-semiconductor capacitors using germanium oxynitride sGeOxNyd as the gate dielectric. Electrical quality was studied using high frequency capacitance–voltage characteristic of epi-Ge showing negligible hysteresis. We discuss the results in terms of Ge–H cluster formation, which lowers the diffusion barrier, allowing for higher diffusivity and surface mobility. The temperature dependence shows tapering off for temperatures exceeding 800 °C, indicating a barrier reduction of ,92 meV. © 2004 American Institute of Physics. [DOI: 10.1063/1.1802381]
File Ge on Si by Novel Heteroepitaxy for High Efficiency Near Infrared Photodetection
Ali K. Okyay, Ammar M. Nayfeh and Krishna C. Saraswat We report germanium-on-silicon MSM photodetectors with responsivities as high as 0.85A/W at 1.55μm and 2V reverse bias, and exhibit reverse dark currents of 100mA/cm2 and external quantum efficiency up to 68%.
File Fabrication of High-Quality p-MOSFET in Ge Grown Heteroepitaxially on Si
Ammar Nayfeh, Chi On Chui, Takao Yonehara, and Krishna C. Saraswat We have successfully demonstrated high-performance p-MOSFETs in germanium grown directly on Si using a novel heteroepitaxial growth technique, which uses multisteps of hydrogen annealing and growth to confine misfit dislocations near the Ge–Si interface, thus not threading to the surface as expected in this 4.2% lattice-mismatched system. We used a low thermal budget process with silicon dioxide on germanium oxynitride (GeO N ) gate dielectric and Si0 75Ge0 25 gate electrode. Characterization of the device using cross-sectional transmission electron microscopy and atomic force microscopy at different stages of the fabrication illustrates device-quality interfaces that yielded hole effective mobility as high as 250 cm2/Vs.
File High-efficiency metal–semiconductor–metal photodetectors on heteroepitaxially grown Ge on Si
File Defect Reduction of Ge on Si by Selective Epitaxy and Hydrogen Annealing
Hyun-Yong Yu, J. Park, A. Okyay and K. Saraswat We demonstrate a promising approach for the monolithic integration of Ge-based nanoelectronics and nanophotonics with Silicon: the selective deposition of Ge on Si by Multiple Hydrogen Annealing for Heteroepitaxy (MHAH). Very high quality Ge layers can be selectively integrated on Si CMOS platform with this technique. We confirm the reduction of dislocation density in Ge layers using transmission electron microscope (TEM) analysis and Schottky diode electrical behavior. In addition, the analysis of the growth directions and the geometrical shape of the resulting films based on the growth conditions provide further insight to the selective Ge growth mechanism
File Low-Temperature, LPCVD and Solid Phase Crystallization of Silicon–Germanium Films
File Effect of Isochronal Hydrogen Annealing on Surface Roughness and Threading Dislocation Density of Epitaxial Ge on Si
Shin-ichi Kobayashi, Y. Nishi and K. C. Saraswat-- We report the effect of hydrogen annealing on the surface roughness and threading dislocation density (TDD) of germanium (Ge) films grown on silicon (Si) substrates by reduced-pressure chemical vapor deposition (RPCVD). The surface roughness initially decreased with an increase in the annealing temperature. At annealing temperatures greater than 650 °C the film thickness varied owing to surface undulations, leading to an increase in the surface roughness. Although high-temperature annealing at 850 °C is effective for reducing TDD, the surface roughness of a 150-nm-thick Ge film annealed at 650 °C reaches a minimum value (~0.7 nm).
File Germanium In Situ Doped Epitaxial Growth on Si for High-Performance n+/p Junction Diode
Hyun-Yong Yu, Szu-Lin Cheng, Peter B. Griffin, Yoshio Nishi, and Krishna C. Saraswat--We demonstrate an abrupt and box-shaped n+/p junction in Ge with a high level of activation of n-type-dopant phosphorus (P) using in situ doping during epitaxial growth. The temperature dependence of dopant activation was investigated associated with the shallower and abrupt junction formation. In addition, we have fabricated high-performance Ge n+/p-junction diodes at 400 ◦C–600 ◦C, based on the in situ doping technique. Excellent diode characteristics having a 1.1 × 104 on/off ratio and a high forward current density (120 A/cm2 at 1 V) are obtained in an n+/p diode at 600-◦C in situ doping.
File Germanium In Situ Doped Epitaxial Growth on Si for High-Performance n+/p-Junction Diode
Hyun-Yong Yu, Masato Ishibashi, Jin-Hong Park, Masaharu Kobayashi, and Krishna C. Saraswat --We successfully demonstrate Ge pMOSFET integrated on Si. In this process, Ge is grown selectively on Si on patterned SiO2 by heteroepitaxy, and pMOSFET is fabricated with gate dielectric stack consisting of thin GeO2 and Al2O3 and Al metal gate electrode. Fabricated devices show ∼80% enhancement over the Si universal hole mobility. These results are promising toward monolithically integrating Ge MOSFETs with Si CMOS VLSI platform.
File High-Efficiency p-i-n Photodetectors on Selective-Area-Grown Ge for Monolithic Integration
Hyun-Yong Yu, S. Ren, W. S. Jung, A. K. Okyay, D. A. B. Miller and K. C. Saraswat -- We demonstrate normal incidence p-i-n photodiodes on selective-area-grown Ge using multiple hydrogen annealing for heteroepitaxy for the purpose of monolithic integration. An enhanced efficiency in the near-infrared regime and the absorption edge shifting to longer wavelength is achieved due to 0.14% residual tensile strain in the selective-area-grown Ge. The responsivities at 1.48, 1.525, and 1.55 μm are 0.8, 0.7, and 0.64 A/W, respectively, without an optimal antireflection coating. These results are promising toward monolithically integrated on-chip optical links and in telecommunications.
File High Performance n-MOSFETs with Novel Source/Drain on Selectively Grown Ge on Si for Monolithic Integration
Hyun-Yong Yu, M. Kobayashi, W. S. Jung, Y. Nishi and K. C. Saraswat -- We demonstrate high performance Ge n-MOSFETs with novel raised source/drain fabricated on high quality Ge selectively grown on Si. S/D regions are formed by in-situ doping process for very low series resistance and abrupt and shallow junctions. The highest Ion for (100) Ge n-MOSFETs to-date is achieved with excellent Ion/Ioff ratio(4x103) and high Ion(3.23μA/µm).
File Effect of isochronal hydrogen annealing on surface roughness and threading dislocation density of epitaxial Ge films grown on Si
Shin-ishi Kobayashia,Y. Nishib, K. C. Saraswat --We report the effect of hydrogen annealing on the surface roughness and threading dislocation density (TDD) of germanium (Ge) films grown on silicon (Si) substrates by reduced-pressure chemical vapor deposition (RPCVD). The surface roughness initially decreased with an increase in the annealing temperature. At annealing temperatures greater than 650 °C the film thickness varied owing to surface undulations, leading to an increase in the surface roughness. Although high-temperature annealing at 850 °C is effective for reducing TDD, the surface roughness of a 150-nm-thick Ge film annealed at 650 °C reaches a minimum value (~ 0.7 nm).
File Low Temperature Germanium Growth on Silicon Oxide Using Boron Seed Layer and In Situ Dopant Activation

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