Definition of Terms Used in Process Steps
Some of the chosen parameters have options that are not obvious to users new to the PlasmaTherms. This is especially true for the RF power and tuning system. Listed are definitions of the options. Special thanks to Jim McVittie for these descriptions.
Plasma-Thermal Recipe RF Matching Modes
The following defines the Plasma-Thermal recipe RF matching modes. 1) Automatic – The matching network is free to move to get to an optimum tuning position. 2) Manual – The matching network goes to a position specified in the recipe and holds there. This may not be an ideal location unless determined with previous testing. 3) Man-Auto – In this mode, the matching network will first drive to the setpoint in the recipe and then switches to “Automatic” mode. 4) Default – This is similar to manual mode wherein the matching network goes to a specified position. The only difference is that the positions are established in the tool configuration screen and not by the recipe set points. 5) Hold – In this mode the matching network will lock into the position at the end of the previous step. If the first step in a recipe has this mode selected then the matching network will lock itself to the position it was in at the end of the previous recipe. For the DSE tool only, the RF generator to the ICP coil switches into its frequency tuning mode when this recipe is selected. Frequency tuning is used to get faster tuning during DSE switching loop cycle. For this mode to work properly, the matching network has to be tuned before the switching loop begins. In the frequency tuning mode, the DSE generator can vary its frequency between 1.9 and 2.1 MHz to minimize reflected power.
Meaning of Bias RF Forward Power and Bias Waveform (PT-DSE)
A number of DSE users have asked me what is the meaning of "Bias RF Forward Power" and "Bias Waveform", which are recipe parameters on thee DSE tool. I am not sure why PT has made it so difficult to understand the meaning of these parameters. Unlike all our other high density etchers, the DSE does not use a RF generator followed by a RF matching network for control the electrode self bias voltage, which controls ion energy. Normally as done on our STS etchers, one specified the bias RF power and observes the self generated DC voltage. Instead, our DSE tool uses what is called a Digital Bias Supply (DBS) to set the RF peak-to-peak voltage (Vpp) at the electrode/wafer. The Comdel DBS, which is the bias supply on our DSE, is a 100KHz 100w supply, which can output a Vpp up to 1500V. In the DSE recipe/parameter table the "Bias RF Forward Power" is the Vpp RF voltage you are requesting the electrode to go to. The DC self-bias is roughly Vpp/2 with this approximation being more accurate at high bias voltages. Now let me explain what the parameter "Bias Waveform" means. In deep silicon etching of SOI wafers, it is found that one can get deep lateral notches at the bottom oxide-silicon corners when one etches down to the buried oxide surface. It is thought that this problem is caused by charging since the bombarding ions and electron have significantly different angular distributions so that the bottoms of holes and trenches charge positively resulting in the positive ions being deflected toward the corners where the notching occurs. To get around this problem, one goes to a pulse modulated low frequency bias power to generate low energy ions and electrons over parts of the etch cycle to neutralize the charging. As pointed out above the DSE uses a 100 KHz supply, which is already low frequency RF. The pulse modulation of the bias is controlled by the "Bias Waveform" number chosen. A value of "1" means that there no modulation so the bias power is applied continuously. A value of "2" means that the bias power is on 25% of the time. I have not measured it but I expect the modulation period to be around 25 ms. Finally, a value of "3" means that the bias is on for 15% of the time. Currently, all the standard etch processes/recipes on the tool use a "bias waveform" setting of "1" (CW) which is reasonable since these processes are not meant for SOI wafers. The SOI process from PT uses a value of "3" (15% duly cycle). We do have a large feature recipe from PT which uses a setting of "2" (25%)