Sidewall epitaxial piezoresistor process and characterisation for in-plane force sensing applications
Etch Profiles
Semiclean Wafers on lampoly/p5000etch Poly
Throttle vs Pressure for SF6 and C4F8
Matlab File: 49 point wafer mapping
Optical Microscopy for Labmembers Working at SNF
Emergency Map (gif)
W-etching-Week3
Hydrochloric Acid 37%
KS Mask Aligner Training
Runsheet for 100nm Thermal Oxidation Test Wafers
Runsheet for 100nm Thermal Oxide Qualification Wafers
This runsheet is to be used to creating 100nm thermal oxide films to be used in the qualification of etch tools and processes. Specifically, these wafers are used primarily in poly etch quals. They may be used for other purposes such as under layers for poly and metal test wafers. This is the same process that is used to qualify tylan1-4 so there may be a ready supply of wafer for use. Check with process staff before proceeding.
It is most time efficient to processes runs of 25 wafers.
STEP 0.10 - STANDARD PRE-DIFFUSION CLEAN
Use ‘L’ stock test wafers.
wbdiff, 5:1:1 H2O:H2O2:NH4OH @ 50°C, 10’
50:1 DI:HF @ Room Temp, 30 sec
5:1:1 DI:H2O2:HCl @ 70°C, 10’
Date _________ Time _________ Operator_________
Comments_____________________________________
STEP 0.20 – THERMAL OXIDATION
Ues 900C, 10:00 dry, 39:00 wet, 10:00 dry time, 100nm oxide.
tylan1 or tylan2 Program ‘WET900’ on Wet Disk..
Date _________ Time _________ Operator _________
Use Nanospec, program 1 (oxide) to measure the center wafer for oxide thickness and uniformity.
System used: qnanospec qnanospec2 qwoolam
T______ TC______ C________ BC________ B________ LC ______ L________ RC________ R________
Thk %Uniformity ______________
Comments______________________________________
If the wafers are going to be used for poly etch processing qualification perform the following lithography steps.
STEP 1.00 - PHOTOMASK #1 - GATE
Use a couple of the wafers to optimize focus and exposure.
STEP 1.10 - SINGE & PRIME
yes standard oven singe/HMDS prime
Date_________ Time _________ Operator _______________
Comments___________________________________________
STEP 1.12 -1.6 micron SPIN COAT RESIST
Apply 1.6 micron of 3612 positive resist w/o VP and 2mm Edge Exclusion, using SVG Coat track program 8 (coat and softbake).
System used: qsvgcoat qsvgcoat2
Date _________ Time _________ Operator ______________
Comments __________________________________________
STEP 1.14 – ALIGNED EXPOSE
Expose using asml stepper:
Job name: ee410LOCOSR1
Layer ID: GATE
Layer Number: 3
Image ID: GATE
Reticle ID: EE410 2008 1
Date _________ Time _________ Operator ______________
Exposure used:_______________________________________
Comments___________________________________________
STEP 1.16 – POST EXPOSE BAKE
Bake using SVG Dev track, bake program 2 (bake only)
System: qsvgdev qsvgdev2
Date _________ Time _________ Operator ______________
Comments___________________________________________
STEP 1.18 - RESIST DEVELOP
Bake using SVG Dev track, programs 4 (develop) and 2 (bake)
System used: qsvgdev qsvgdev2
Date________ Time _________ Operator ________________
Comments___________________________________________
STEP 1.20 – VISUAL INSPECTION
Visual and microscope inspection. Check for defects, alignment and exposure quality.
Wafers inspected ______ ______ ______ ______ ______
Date _________ Time _________ Operator ______________
Comments __________________________________________
REWORK DONE?
qyes qno
Wafers reworked: ____________________________________
If yes, attach REWORK sheet here.
Return all the wafers, patterned and unpatterned to the same storage box and mark appropriately.
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