Skip to content. | Skip to navigation

Sections
Personal tools
You are here: Home / Process / Runsheets / Runsheets for Etch Qualification Test Wafers / Runsheet for 1um LTO Test Wafers

Runsheet for 1um LTO Test Wafers

This page describes the step needed to create 1um thermal oxide wafers used in the qualification and characterization of etch processes.

Runsheet for LTO Qualification Wafers

 

This runsheet is to be used to creating 1um thermal oxide films to be used in the qualification of etch tools and processes.  Specifically, these wafers are used primarily in oxide etch quals. 

 

It is most time efficient to processes runs of 25 wafers.

 

 STEP 0.10 - STANDARD PRE-DIFFUSION CLEAN  

Use ‘L’ stock test wafers. 

 

wbdiff, 5:1:1 H2O:H2O2:NH4OH @ 50°C, 10’

5:1:1  DI:H2O2:HCl @ 70°C, 10’

50:1 DI:HF @ Room Temp, 30 sec

Date _________  Time      _________      Operator_________

Comments_____________________________________

 

 

STEP 0.20 – LOW TEMP OXIDATION (LTO)

Ues 450C, 01:40:00 dep time, 1um oxide.

 

tylanbpsg  Program ‘LTO450’ on LTO Disk.. 

 

Date _________    Time    _________  Operator    _________

 

Use Nanospec, program 1 (oxide) to measure the center wafer for oxide thickness and uniformity.

 

System used:             qnanospec       qnanospec2       qwoolam

T______ TC______  C________  BC________  B________ LC ______  L________  RC________  R________

Thk %Uniformity ______________

Comments______________________________________

 

 

STEP 1.00 - PHOTOMASK #1 - CONTACT

Use a couple of the wafers to optimize focus and exposure.

 

STEP 1.10 - SINGE & PRIME

yes standard oven singe/HMDS prime

 

Date_________  Time  _________  Operator  _______________

 

Comments___________________________________________

 

STEP 1.12 -1.6 micron SPIN COAT RESIST

Apply 1.6 micron of 3612 positive resist w/o VP and 2mm Edge Exclusion, using SVG Coat track program 8 (coat and softbake).

 

System used:  qsvgcoat      qsvgcoat2

 

Date _________  Time  _________  Operator  ______________

 

Comments __________________________________________

 

STEP 1.14 – ALIGNED EXPOSE

Expose using asml stepper:

Job name:  ee410LOCOSR1

Layer ID:  CONTACT

Layer Number:  6

Image ID:  CONTACT

Reticle ID:  EE410 2008 2

 

Date _________  Time  _________   Operator  ______________

 

Exposure used:_______________________________________

 

Comments___________________________________________

 

STEP 1.16 – POST EXPOSE BAKE

Bake using SVG Dev track, bake program 2 (bake only)

 

System:  qsvgdev              qsvgdev2

 

Date _________  Time  _________  Operator  ______________

 

Comments___________________________________________

 

STEP 1.18 - RESIST DEVELOP

Bake using SVG Dev track, programs 4 (develop) and 2 (bake)

 

System used:  qsvgdev      qsvgdev2

 

Date________  Time  _________  Operator  ________________

 

Comments___________________________________________

 

STEP 1.20 – VISUAL INSPECTION

Visual and microscope inspection.  Check for defects, alignment and exposure quality. 

 

Wafers inspected  ______   ______   ______   ______   ______

 

Date _________  Time  _________  Operator  ______________

 

Comments __________________________________________

 

REWORK DONE?

             qyes                 qno

 

Wafers reworked:  ____________________________________

If yes, attach REWORK sheet here.

 

 

Return all the wafers, patterned and unpatterned to the same storage box and mark appropriately.

Document Actions